Electrode and method of forming the electrode

Abstract

An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier ( 1 ) provided with an insulating layer ( 7 ) which is patterned at a front side. Conducting material in an electrode layer ( 4 ) is applied in the cavities of the patterned insulating layer and in contact with the carrier. An connection layer ( 5 ) is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.

1 - 244 . (canceled) 
     
     
         245 . A master electrode for forming an electrochemical cell with a substrate, comprising:
 a carrier of at least one layer of a conducting and/or semi-conducting material, said carrier at a front side being provided with several recesses and at least one layer of an insulating pattern layer being arranged between the recesses,   wherein each recess in said at least one layer of a conducting and/or semi-conducting material comprises a bottom surface and side surfaces, and said side surfaces being provided with at least one layer of an insulating material,   wherein said bottom surface is provided with at least one layer of a conducting electrode layer of an electrode forming, conducting material.   
     
     
         246 . The master electrode of  claim 245 , wherein said carrier comprises a back side provided with at least one layer of an insulating material, said insulating material comprising at least one recess forming a connection. 
     
     
         247 . The master electrode of  claim 246 , wherein said recess forming a connection is provided with at least one conducting electrode layer. 
     
     
         248 . The master electrode of  claim 245 , wherein said carrier is made from at least one layer of a conducting and/or semi-conducting material and is provided with a conducting electrode layer of a electrode forming, conducting material in cavities of said insulating pattern layer. 
     
     
         249 . The master electrode of  claim 245 , further comprising contacts means for engaging a substrate surface when the electrode is applied to said substrate for forming electrical contact with said substrate surface. 
     
     
         250 . The master electrode of  claim 249 , wherein said contact means is arranged at the peripheral surface of the carrier outside said insulating material. 
     
     
         251 . The master electrode of  claim 245 , wherein the disc is made from an elastic and/or flexible material. 
     
     
         252 . The master electrode of  claim 245 , wherein an anode material is predeposited in cavities of the insulating pattern layer in contact with said conducting electrode layer. 
     
     
         253 . The master electrode of  claim 245 , further comprising an adhesion layer applied onto at least some parts of the carrier prior to applying said conducting electrode layer, wherein said adhesion layer is comprised of one or more materials that increase the adhesion of the conducting electrode layer to said carrier. 
     
     
         254 . The master electrode of  claim 245 , further comprising an adhesion layer is arranged onto at least some parts of said carrier prior to arranging said insulating pattern layer, wherein said adhesion layer comprise at least one layer of material that improves the adhesion properties between the insulating pattern layer and the carrier. 
     
     
         255 . The master electrode of  claim 245 , further comprising an etch-stop layer, which is applied prior to applying said insulating pattern layer. 
     
     
         256 . The master electrode of  claim 245 , wherein the insulating pattern layer comprises one or more layers of at least one material having properties such that the side walls of the cavities of the insulating pattern layer are hydrophilic and the top of the insulating pattern layer is hydrophobic. 
     
     
         257 . The master electrode of  claim 245 , wherein said insulating pattern layer is comprised of at least one layer of a flexible material or of at least one layer of rigid material and at least one layer of a flexible material. 
     
     
         258 . The master electrode of  claim 257 , wherein said at least one layer of flexible material is arranged on top of said at least one layer of rigid material. 
     
     
         259 . The master electrode of  claim 245 , wherein said carrier or disc has a circular shape or a rectangular shape. 
     
     
         260 . The master electrode of  claim 245 , wherein the carrier or disc is provided with recesses in the same region as recesses of the insulating pattern layer, said recesses of the carrier or disc being provided with a conducting electrode layer. 
     
     
         261 . The master electrode of  claim 245 , wherein said insulating pattern layer is provided by bonding and patterning a bond-layer of an insulating material onto said carrier. 
     
     
         262 . The master electrode of  claim 245 , further comprising connection sites as recesses or holes that allow for an external electrical connection to a substrate. 
     
     
         263 . The master electrode of  claim 262 , wherein said carrier or disc is provided with at least one recess or hole in the perimeter or close to the perimeter. 
     
     
         264 . The master electrode of  claim 245 , further comprising an electrical seed layer connection of a conducting, electrode forming material and being arranged in at least some parts between the recesses on top of said insulating pattern layer,
 wherein said electrical seed layer connection is electrically isolated by an insulating material from the conducting or semiconducting materials of the carrier, disc, conducting electrode layer, or connection layer.   
     
     
         265 . The master electrode of  claim 264 , wherein said electrical seed layer connection is provided as a layer around an edge of the carrier or disc. 
     
     
         266 . The master electrode of  claim 264 , wherein different portions of said electrical seed layer connection are provided with connection areas at the back side of the carrier and through the carrier. 
     
     
         267 . The master electrode of  claim 245 , further comprising alignment marks for aligning said master electrode to a substrate;
 said alignment marks comprising structures or cavities in a layer on the front side and/or back side of the master electrode.   
     
     
         268 . The master electrode of  claim 245 , wherein said carrier and the conducting electrode layer include a protruding structure extending in at least one cavity of an insulating pattern layer; and
 a predeposited anode material is arranged onto said conducting electrode layer.   
     
     
         269 . A method of forming a master electrode, comprising:
 providing a carrier of at least one layer of a conducting and/or semi-conducting material;   providing recesses in said layer of a conducting and/or semi-conducting material;   providing at least one insulating pattern layer between the recesses, further comprising:   providing at least one layer of an insulating material at side surfaces of said at least one recess, and   providing at least one layer of a conducting electrode layer at a bottom surface of said at least one recess.   
     
     
         270 . The method of  claim 269 , wherein the insulated material is applied by a method selected from the group comprising: thermal oxidation, thermal nitridation, sputtering, PECVD, and ALD. 
     
     
         271 . The method of  claim 270 , wherein the insulated material is removed by anisotropic etching having a higher etch rate in a direction normal to said bottom surfaces than in a direction normal to said side surfaces of the recesses. 
     
     
         272 . The method of  claim 270 , wherein the insulated material is removed from the bottom surfaces of the recesses by lithography and etching. 
     
     
         273 . The method of  claim 269 , further comprising predpositing an anode material in cavities of the insulating pattern layer in contact with said conducting electrode layer,
 wherein said anode material is predeposited with a method selected from the group comprising: electroplating, electroless plating, immersion plating, CVD, MOCVD, (charged) powder-coating, chemical grafting, electrografting, and combinations thereof.   
     
     
         274 . The method of  claim 269 , wherein the insulating material is applied with a method selected from the group comprising: thermo-oxidation, Plasma-Enhanced-Chemical-Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), Chemical-Vapor-Deposition (CVD), electrical anodization, Atomic-Layer-Deposition (ALD), spin-coating, spray-coating, roller-coating, powder-coating, adhesive taping, pyrolysis, bonding and combinations thereof. 
     
     
         275 . The method of  claim 269 , further comprising performing a planarization step on said carrier. 
     
     
         276 . The method of  claim 269 , wherein said conducting electrode layer is applied with methods selected from the group comprising: ALD, Metallorganic-Chemical-Vapor-Deposition (MOCVD), PVD, CVD, sputtering, electroless deposition, immersion deposition, electrodeposition, electro-grafting, chemical grafting, and combinations thereof. 
     
     
         277 . The method of  claim 269 , wherein said conducting electrode layer is treated by thermal methods selected from the group comprising: rapid-thermal-annealing (RTA), furnace heating, hot-plate heating, and combinations thereof. 
     
     
         278 . The method of  claim 277 , wherein said conducting electrode layer is formed by applying several layers of at least one material and by treating at least one layer by said thermal methods before applying a next layer. 
     
     
         279 . The method  claim 269 , further comprising arranging an adhesion layer onto at least some parts of said carrier prior to arranging said insulating pattern layer;
 wherein said adhesion layer comprises at least one layer of material that improves the adhesion properties between the insulating pattern layer and the carrier,   wherein said adhesion layer is applied using deposition methods selected from the group comprising: electrodeposition, spin-coating, spray-coating, dip-coating, Molecular-Vapor-Deposition (MVD), ALD, MOCVD, CVD, PVD, sputtering, electroless deposition, immersion deposition, electrografting, chemical grafting, and combinations thereof.   
     
     
         280 . The method of  claim 269 , further comprising performing a planarization step on the arranged insulating pattern layer, wherein said planarization step is performed by a method selected from the group comprising: chemical-mechanical-polishing (CMP), lapping, contact planarization (CP) and/or dry etching methods such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling, and combinations thereof. 
     
     
         281 . The method of  claim 269 , further comprising forming recesses in said insulating pattern layer by using lithography, etching methods, and/or mechanical abrasive methods. 
     
     
         282 . The method of  claim 281 , wherein said etching methods comprise arranging a patterned etch-mask onto at least some areas of said insulating pattern layer, said areas being protected from etching,
 wherein said patterned etch-mask is produced by lithography and/or etching methods,   wherein said etch-mask is comprised of a polymer resist used in said lithographical methods or a hard-mask.   
     
     
         283 . The method of claim  293 , wherein said etch-mask comprises at least one structure layer forming in said at least one electrochemical cell formed by a further master electrode. 
     
     
         284 . The method of  claim 269 , further comprising:
 using a damascene process to create the cavities of said insulating pattern layer, said damascene process involving applying a sacrificial pattern layer, having recesses, onto the carrier;   applying an insulating material so that it covers said sacrificial pattern layer and up the recesses of the sacrificial pattern;   planarizing said insulating material until the sacrificial pattern layer is uncovered; and   removing said sacrificial pattern layer whereby an insulating pattern layer is formed, wherein said sacrificial pattern is arranged by applying a material which is patterned by lithography, plating, and/or etching methods or said sacrificial pattern layer comprises at least one structure layer being formed in an electrochemical cell with a further master electrode.   
     
     
         285 . The method of  claim 269 , further comprising coating a release layer onto at least some parts of the insulating pattern layer. 
     
     
         286 . The method of  claim 269 , further comprising treating at least some surfaces of said insulating pattern layer with thermal treatment, oxygen/nitrogen/argon plasma treatment, surface conversion for anti-sticking (SURCAS), strong oxidizing agents, or combinations thereof. 
     
     
         287 . The method of  claim 269 , further comprising:
 forming the insulating pattern layer with lithographical and/or etching methods;   creating cavities reaching down to the carrier or conducting electrode;   patterning the insulating pattern layer once more in at least some areas; and   creating cavities that compensate for topography on the substrate but do not reach the carrier or conducting electrode layer.   
     
     
         288 . The method of  claim 269 , wherein said insulating pattern layer is patterned by repeating lithography and/or etching steps and thereby creating multiple levels of cavities so as to compensate for multiple levels of topography of different heights and shapes on a substrate.