Chip package structure and method of making the same

Abstract

A chip package structure and method thereof uses a semiconductor substrate as a package substrate, which improve heat dissipation. Also, the chip package structure is incorporated with a planarization structure, which renders the chip and the package substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, electrical connections in series or in parallel between chips can be easily implemented by virtue of the planar patterned conductive layer.

1 . A method of fabricating a chip package, comprising:
 providing a package substrate, and forming a plurality of concave chip mounting areas on an upper surface of the package substrate;   providing a plurality of chips, each of the chips comprising:
 an element substrate; 
 an element disposed on the element substrate; and 
 at least a first connecting pad and at least a second connecting pad disposed on an upper surface of the element; 
   mounting a lower surface of the element substrate of each of the chips within each of the chip mounting areas;   forming a planarization structure on the package substrate and the chips, and forming a plurality of contact holes in the planarization structure, wherein a portion of the first connecting pad and a portion of the second connecting pad of each of the chips are exposed by the contact holes; and   forming an upper patterned conductive layer on the planarization structure, wherein the upper patterned conductive layer is filled into the contact holes, and the upper patterned conductive layer is electrically connected to the first connecting pad and the second connecting pad of each of the chips.   
     
     
         2 . The method of  claim 1 , wherein the package substrate comprises a semiconductor substrate. 
     
     
         3 . The method of  claim 1 , further comprising forming a plurality of through holes in the package substrate before mounting the lower surface of the element substrate of each of the chips within each of the chip mounting areas. 
     
     
         4 . The method of  claim 3 , wherein the step of forming the through holes in the package substrate comprises:
 forming a plurality of upper through holes on the upper surface of the package substrate; and   forming a plurality of lower through holes corresponding to the upper through holes on a lower surface of the package substrate, so that the upper through holes and the corresponding lower through holes form the through holes.   
     
     
         5 . The method of  claim 4 , wherein the upper through holes are formed by an anisotropic wet etching process. 
     
     
         6 . The method of  claim 5 , wherein the chip mounting areas and the upper through holes are formed by the same anisotropic wet etching process. 
     
     
         7 . The method of  claim 4 , wherein the lower through holes are formed by an anisotropic wet etching process. 
     
     
         8 . The method of  claim 4 , further comprising forming a back patterned conductive layer on the lower surface of the package substrate and filling the back patterned conductive layer into the lower through holes. 
     
     
         9 . The method of  claim 8 , wherein the planarization structure exposes the upper through holes, the upper patterned conductive layer is filled into the upper through holes, and is electrically connected to the back patterned conductive layer. 
     
     
         10 . The method of  claim 1 , wherein the depth of the chip mounting areas and the thickness of the chip are substantially the same. 
     
     
         11 . The method of  claim 1 , wherein the planarization structure comprises a photosensitive material layer and the planarization structure is patterned by an exposure-and-development process. 
     
     
         12 . The method of  claim 1 , wherein the upper patterned conductive layer comprises a plurality of first upper patterned conductive layers and a plurality of second upper patterned conductive layers, each of the first upper patterned conductive layers is electrically connected to the first connecting pad of each of the chips and each of the second upper patterned conductive layers is electrically connected to the second connecting pad of each of the chips. 
     
     
         13 . The method of  claim 1 , wherein the chips comprises a first chip and a second chip, the upper patterned conductive layer comprises a first upper patterned conductive layer and a second upper patterned conductive layer, the first upper patterned conductive layer is electrically connected to the first connecting pad of the first chip and the second connecting pad of the second chip, and the second upper patterned conductive layer is electrically connected to the second connecting pad of the first chip and the first connecting pad of the second chip, so that the first chip and the second chip are electrically connected in series. 
     
     
         14 . The method of  claim 1 , wherein the chips comprises a first chip and a second chip, the upper patterned conductive layer comprises a first upper patterned conductive layer and a second upper patterned conductive layer, the first upper patterned conductive layer is electrically connected to the first connecting pad of the first chip and the first connecting pad of the second chip, and the second upper patterned conductive layer is electrically connected to the second connecting pad of the first chip and the second connecting pad of the second chip, so that the first chip and the second chip are electrically connected in parallel. 
     
     
         15 . The method of  claim 1 , wherein each of the chips comprises a light emitting diode (LED) chip, and the element comprises a first conductive type doped semiconductor layer, a second conductive type doped semiconductor layer, and a light emitting layer disposed in between the first conductive type doped semiconductor layer and the second conductive type doped semiconductor layer. 
     
     
         16 . A chip package, comprising:
 a package substrate comprising at least a concave chip mounting area disposed on an upper surface of the package substrate;   at least a chip disposed within the chip mounting area, wherein the chip comprises:
 an element substrate mounted on the package substrate; 
 an element disposed on the element substrate; and 
 at least a first connecting pad and at least a second connecting pad disposed on an upper surface of the element; 
   a planarization structure, having a planar surface, disposed on the package substrate and the chip, the planarization structure comprising a plurality of contact holes, wherein the first connecting pad and the second connecting pad are exposed by the contact holes; and   an upper patterned conductive layer disposed on the planarization structure, wherein the upper patterned conductive layer is filled into the contact holes, and the upper patterned conductive layer is electrically connected to the first connecting pad and the second connecting pad of the chip.   
     
     
         17 . The chip package of  claim 16 , wherein the package substrate comprises a semiconductor substrate. 
     
     
         18 . The chip package of  claim 16 , wherein the package substrate comprises a plurality of through holes disposed outside of the chip mounting area. 
     
     
         19 . The chip package of  claim 18 , wherein each of the through holes comprises an upper through hole and a lower through hole corresponding to the upper through hole. 
     
     
         20 . The chip package of  claim 19 , wherein the upper through hole and the lower through hole each comprises an outwardly-inclined side wall. 
     
     
         21 . The chip package of  claim 19 , further comprising a back patterned conductive layer disposed on a lower surface of the package substrate, and the back patterned conductive layer is filled into the lower through holes. 
     
     
         22 . The chip package of  claim 21 , wherein the planarization structure exposes the upper through holes, the lower patterned conductive layer is filled into the upper through holes, and electrically connected to the back patterned conductive layer. 
     
     
         23 . The chip package of  claim 16 , wherein the depth of the chip mounting area and the thickness of the chip are substantially the same. 
     
     
         24 . The chip package of  claim 16 , wherein the upper patterned conductive layer comprises a first upper patterned conductive layer and a second upper patterned conductive layer, the first upper patterned conductive layer is electrically connected to the first connecting pad of the chip, and the second upper patterned conductive layer is electrically connected to the second connecting pad of the chip. 
     
     
         25 . The chip package of  claim 16 , wherein the at least one chip comprises a first chip and a second chip, the upper patterned conductive layer comprises a first upper patterned conductive layer and a second upper patterned conductive layer, the first upper patterned conductive layer is electrically connected to the first connecting pad of the first chip and the second connecting pad of the second chip, and the second upper patterned conductive layer is electrically connected to the second connecting pad of the first chip and the first connecting pad of the second chip, so that the first chip and the second chip are electrically connected in series. 
     
     
         26 . The chip package of  claim 16 , wherein the at least one chip comprises a first chip and a second chip, the upper patterned conductive layer comprises a first upper patterned conductive layer and a second upper patterned conductive layer, the first upper patterned conductive layer is electrically connected to the first connecting pad of the first chip and the first connecting pad of the second chip, and the second upper patterned conductive layer is electrically connected to the second connecting pad of the first chip and the second connecting pad of the second chip, so that the first chip and the second chip are electrically connected in parallel. 
     
     
         27 . The chip package of  claim 16 , wherein the chip comprises a light emitting diode (LED) chip, and the element comprises a first conductive type doped semiconductor layer, a second conductive type doped semiconductor layer, and a light emitting layer disposed in between the first conductive type doped semiconductor layer and the second conductive type doped semiconductor layer. 
     
     
         28 . A method of fabricating a chip package, comprising:
 providing a package substrate, and forming a plurality of concave chip mounting areas on an upper surface of the package substrate;   forming a lower patterned conductive layer on the upper surface of the package substrate, wherein the lower patterned conductive layer comprises a plurality of first lower patterned conductive layers and a plurality of second lower patterned conductive layers;   providing a plurality of chips, each of the chips comprising:
 a conductive substrate; 
 an element disposed on the conductive substrate; and 
 a first connecting pad disposed on an upper surface of the element; 
   mounting a lower surface of the conductive substrate of each of the chips within each of the chip mounting areas, and electrically connecting the conductive substrate of each of the chips to each of the second lower patterned conductive layer;   forming a planarization structure on the package substrate and the chips, and forming a plurality of contact holes in the planarization structure, wherein a portion of the first connecting pad of each of the chips and the first lower patterned conductive layers are exposed by the contact holes; and   forming an upper patterned conductive layer on the planarization structure, wherein the upper patterned conductive layer is filled into the contact holes, so that each of the first lower patterned conductive layers of the lower patterned conductive layer is electrically connected to the first connecting pad of each of the chips via the upper patterned conductive layer.   
     
     
         29 . The method of  claim 28 , wherein the package substrate comprises a semiconductor substrate. 
     
     
         30 . The method of  claim 28 , further comprising forming a plurality of through holes in the package substrate before mounting the lower surface of the conductive substrate of each of the chips in each of the chip mounting areas. 
     
     
         31 . The method of  claim 30 , wherein the step of forming the through holes in the package substrate comprises:
 forming a plurality of upper through holes on the upper surface of the package substrate; and   forming a plurality of lower through holes corresponding to the upper through holes on a lower surface of the package substrate, so that the upper through holes and the corresponding lower through holes form the through holes.   
     
     
         32 . The method of  claim 31 , wherein the upper through holes are formed by an anisotropic wet etching process. 
     
     
         33 . The method of  claim 32 , wherein the chip mounting areas and the upper through holes are formed by the same anisotropic wet etching process. 
     
     
         34 . The method of  claim 31 , wherein the lower through holes are formed by an anisotropic wet etching process. 
     
     
         35 . The method of  claim 31 , further comprising forming a back patterned conductive layer on the lower surface of the package substrate, filling the back patterned conductive layer into the lower through holes, and filling the lower patterned conductive layer into the upper through holes so that the lower patterned conductive layer and the back patterned conductive layer are electrically connected. 
     
     
         36 . The method of  claim 28 , wherein the depth of the chip mounting areas and the thickness of the chip are substantially the same. 
     
     
         37 . The method of  claim 28 , wherein the planarization structure comprises a photosensitive material layer and the planarization structure is patterned by an exposure-and-development process. 
     
     
         38 . The method of  claim 28 , wherein the upper patterned conductive layer comprises a plurality of web electrode patterns corresponding to the chip mounting areas respectively. 
     
     
         39 . The method of  claim 28 , wherein the step of forming the upper patterned conductive layer further comprises electrically connecting the first connecting pad of the chip of one of the chip mounting areas to the second lower patterned conductive layer of another chip mounting area via the upper patterned conductive layer, so that the two chips are electrically connected in series. 
     
     
         40 . The method of  claim 28 , wherein the step of forming the upper patterned conductive layer further comprises electrically connecting the first connecting pad of the chip of one of the chip mounting areas to the first lower patterned conductive layer of another chip mounting area via the upper patterned conductive layer, so that the two chips are electrically connected in parallel. 
     
     
         41 . The method of  claim 28 , wherein the chip comprises a light emitting diode (LED) chip and the element comprises a first conductive type doped semiconductor layer, a second conductive type doped semiconductor layer, and a light emitting layer disposed in between the first conductive type doped semiconductor layer and the second conductive type doped semiconductor layer. 
     
     
         42 . A chip package, comprising:
 a package substrate comprising at least a concave chip mounting area disposed on an upper surface of the package substrate;   a lower patterned conductive layer disposed on the upper surface of the package substrate, wherein the lower patterned conductive layer comprises at least a first lower patterned conductive layer and at least a second lower patterned conductive layer;   at least a chip disposed in the chip mounting area, wherein the chip comprises:
 a conductive substrate disposed on the second lower patterned conductive layer; 
 an element disposed on the conductive substrate; and 
 a first connecting pad disposed on an upper surface of the element; 
   a planarization structure, having a planar surface, disposed on the package substrate, the chip and the lower patterned conductive layer, the planarization structure comprising a plurality of contact holes, wherein the first connecting pad and the first lower patterned conductive layer are exposed by the contact holes; and   an upper patterned conductive layer disposed on the planarization structure, wherein the upper patterned conductive layer is filled into the contact holes, so that the first lower patterned conductive layer of the lower patterned conductive layer is electrically connected to the first connecting pad of the chip via the upper patterned conductive layer.   
     
     
         43 . The chip package of  claim 42 , wherein the package substrate comprises a semiconductor substrate. 
     
     
         44 . The chip package of  claim 42 , wherein the package substrate further comprises a plurality of through holes disposed outside of the chip mounting area, and the lower patterned conductive layer is electrically connected to a lower surface of the package substrate via the through holes. 
     
     
         45 . The chip package of  claim 44 , wherein each of the through holes comprises an upper through hole and a lower through hole corresponding to the upper through hole. 
     
     
         46 . The chip package of  claim 45 , wherein the upper through hole and the lower through hole each comprises an outwardly-inclined side wall. 
     
     
         47 . The chip package of  claim 45 , wherein the lower surface of the package substrate comprises a back patterned conductive layer, the back patterned conductive layer is filled into the lower through holes, and the lower patterned conductive layer is filled into the upper through holes so as to electrically connect to the back patterned conductive layer. 
     
     
         48 . The chip package of  claim 42 , wherein the depth of the chip mounting area and the thickness of the chip are substantially the same. 
     
     
         49 . The chip package of  claim 42 , wherein the upper patterned conductive layer comprises a web electrode pattern corresponding to the chip mounting area. 
     
     
         50 . The chip package of  claim 42 , further comprising another chip disposed in another chip mounting area, wherein the first connecting pad of the chip of the chip mounting area is electrically connected to the second lower patterned conductive layer of another chip mounting area via the upper patterned conductive layer, such that the two chips are electrically connected in series. 
     
     
         51 . The chip package of  claim 42 , further comprising another chip disposed in another chip mounting area, wherein the first connecting pad of the chip of the chip mounting area is electrically connected to the first lower patterned conductive layer of another chip mounting area via the upper patterned conductive layer, such that the two chips are electrically connected in parallel. 
     
     
         52 . The chip package of  claim 42 , wherein the chip comprises a light emitting diode (LED) chip and the element comprises a first conductive type doped semiconductor layer, a second conductive type doped semiconductor layer, and a light emitting layer disposed in between the first conductive type doped semiconductor layer and the second conductive type doped semiconductor layer.