US2009300558A1PendingUtilityA1

Use of state nodes for efficient simulation of large digital circuits at the transistor level

Assignee: NAT SEMICONDUCTOR CORPPriority: Aug 8, 2005Filed: Jun 12, 2009Published: Dec 3, 2009
Est. expiryAug 8, 2025(expired)· nominal 20-yr term from priority
G06F 30/33
50
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Claims

Abstract

A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state.

Claims

exact text as granted — not AI-modified
1 . A method of representing the state of a sequential digital integrated circuit, the method comprising:
 identifying the state (logic value) of all state nodes in the circuit; and   identifying the state of all sequential submodules of the circuit.   
   
   
       2 . A method of simulating a sequential digital circuit module given a set of input conditions and a current state, the method comprising:
 initializing all state nodes of the circuit module to logic values stored in the current state;   initializing all sequential submodules of the circuit module to the states stored in the current state;   simulating the circuit module after initialization;   after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential submodules in the next state of the circuit module, multiple value changes in the state nodes of the circuit module being recorded in the next state.   
   
   
       3 . A machine-readable medium having stored thereon sequences of instructions for implementing a method of representing the state of a sequential digital integrated circuit, the instruction sequences including instructions that, when executed by a data processing system, cause the data processing system to perform:
 identifying the state (logic value) of all state nodes in the circuit; and   identifying the state of all sequential submodules of the circuit.   
   
   
       4 . A machine-readable medium having stored thereon sequences of instructions for implementing a method of simulating a sequential digital circuit module given a set of input conditions and a current state, the instructions sequences including instructions that, when executed by a data processing system, cause the data processing system to perform:
 initializing all state nodes of the circuit module to logic values stored in the current state;   initializing all sequential submodules of the circuit module to the states stored in the current state;   simulating the circuit module after initialization; and   after completion of the simulation step, reporting the ouput logic values and associated delays and storing the logic values of the state nodes and the states of the sequential submodules in the next state of the circuit module, multiple value changes in the state nodes of the circuit module being recorded in the next state.

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