Methods for Wafer Scale Processing of Needle Array Devices

Abstract

Methods of fabricating needle arrays on a wafer scale include etching a wafer of columns and needles and coating the same with an electrically insulating material and exposing electrically conductive tips. This process can benefit from using a slow spin speed to distribute resist material across the wafer before etching and using a carrier wafer to support singulated arrays to allow full coverage of upper array surfaces with electrically insulating materials. These processes allow for efficient high volume production of high count microelectrode arrays with a high repeatability and accuracy.

1 . A method for wafer-scale fabrication of needle arrays comprising:
 (a) providing a wafer having an upper surface and a lower surface;   (b) mechanically modifying the upper surface to produce a plurality of vertically-extending columns;   (c) etching the wafer to produce a plurality of needles from the plurality of vertically-extending columns;   (d) coating tips of the plurality of needles with an electrically conductive coating;   (e) securing a carrier substrate to the lower surface of the wafer;   (d) separating the wafer into a plurality of individual needle arrays, each having at least one edge, while leaving the carrier substrate intact;   (g) encapsulating the individual needle arrays with an electrically insulative coating so that each edge is covered by the electrically insulative coating; and   (h) de-encapsulating the tips of the plurality of needles.   
     
     
         2 . The method of  claim 1 , wherein etching the wafer includes a first dynamic etching to form rounded columns, followed by static etching to form the plurality of needles having sharpened tips. 
     
     
         3 . The method of  claim 2 , wherein etching the wafer comprises the steps:
 (a) placing the wafer on a vacuum holder; and   (b) spinning the wafer while in contact with an etching solution.   
     
     
         4 . The method of  claim 3 , wherein before coating, the plurality of needles are encompassed in a resist material to a depth that exposes the tip of each needle to a predetermined tip length to be coated with the electrically conductive coating. 
     
     
         5 . The method of  claim 4 , further comprising placing the wafer in a vacuum to encourage bubble elimination from the resist material prior to curing of the resist material. 
     
     
         6 . The method of  claim 4 , wherein the resist material is applied by spin coating at a low spin speed. 
     
     
         7 . The method of  claim 6 , wherein the depth is controlled by controlling the spin speed. 
     
     
         8 . The method of  claim 7 , wherein the spin speed is from about 20 rpm to about 500 rpm. 
     
     
         9 . The method of  claim 4 , wherein the tip length is substantially uniform across needles. 
     
     
         10 . The method of  claim 9 , wherein a degree of tip length uniformity is within about 50% of the tip length. 
     
     
         11 . The method of  claim 4 , further comprising stripping the resist material from the needles after coating. 
     
     
         12 . The method of  claim 4 , wherein the tips of the plurality of needles define a non-planar surface to which a top layer of the resist material conforms. 
     
     
         13 . The method of  claim 1 , wherein de-encapsulating the tips of the plurality of needles comprises:
 (a) encompassing the needles in a resist material leaving the tips exposed to a predetermined tip length; and   (b) applying a further processing step to remove the electrically insulative coating from the tips.   
     
     
         14 . The method of  claim 13 , wherein the further processing step is oxygen plasma etching. 
     
     
         15 . The method of  claim 13 , wherein the further processing is laser ablation. 
     
     
         16 . The method of  claim 1 , wherein mechanically modifying includes:
 (a) forming channels in the lower surface to form a grid of electrode bases;   (b) filling the channels with an electrically insulating material to form an electrically insulating network; and   (c) forming a complimentary set of channels on the upper surface opposite the channels in the lower surface to form the plurality of vertically-extending columns.   
     
     
         17 . The method of  claim 16 , wherein the electrically insulating material is epoxy or glass. 
     
     
         18 . The method of  claim 16 , further comprising forming metal contacts on each of the electrode bases, said metal contacts being electrically isolated from one another. 
     
     
         19 . The method of  claim 16 , wherein the channels in the lower surface and the complimentary set of channels are formed by wire EDM or dicing. 
     
     
         20 . The method of  claim 1 , wherein the second wafer is removed subsequent to de-encapsulating the tips. 
     
     
         21 . The method of  claim 1 , wherein the carrier substrate is left in place.