Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer

Abstract

The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

1 . An electrical apparatus wherein first and second different types of circuitry are interconnected into a functional electrical apparatus unit,
 the improvement comprising:   an interface supporting substrate member of dielectric material having first and second essentially parallel planar surfaces,
 said first type of circuitry being positioned on said first planar surface of said substrate member, 
 said second type of circuitry positioned on said second planar surface of said substrate member,
 said substrate further having a plurality of electrical pathways from said first planar surface to said second planar surface through said dielectric material, 
 
 a plurality of electrical pathways through said dielectric material joining circuit locations in said first and second types of circuitry, and,
 said electrical pathways through said dielectric material being filled with chemically deposited metal. 
 
   
   
   
       2 . The improvement of  claim 1  wherein said dielectric material is silicon. 
   
   
       3 . The improvement of  claim 2  wherein said electrical pathways are surrounded with an adhesion promoting layer. 
   
   
       4 . The improvement of  claim 3  wherein said adhesion promoting layer is a reaction product of Pd and Cu. 
   
   
       5 . The improvement of  claim 3  wherein said adhesion promoting layer is selected from the group consisting of Ta, TaN, a Pd catalytic layer and combinations thereof. 
   
   
       6 . The improvement of  claim 1  where said chemically deposited metal is electroless plated metal. 
   
   
       7 . The improvement of  claim 6  wherein said electroless deposited metal is selected from the group consisting of Ni, Co, Cu, Au and combinations thereof. 
   
   
       8 . The method of providing an interface supporting substrate with electrical pathways through said substrate for use between entities of different circuitry in electrical apparatus,
 comprising in combination the steps of:   providing a wafer structure of dielectric material having first and second area surfaces separated by a distance of the material of said wafer,   forming an array of via openings through said first area surface into said material of said wafer, said via openings ending blind at a depth less than said distance,   providing a chemical metal deposition promoting adhesion coating on at least the walls of said blind via openings,   filling said blind via openings with chemically deposited metal,
 removing all material from said first area surface thereby planarizing said via openings, and, 
 removing said material of said wafer through said second area surface until said filled vias are exposed and said second surface is planarized. 
   
   
   
       9 . The method of  claim 8  where said distance is said electrical pathway design length. 
   
   
       10 . The method of  claim 9  where said material of said wafer is silicon. 
   
   
       11 . The method of  claim 10  wherein said chemical deposited metal is by electroless plating. 
   
   
       12 . The method of  claim 11  wherein said metal is selected from the group consisting of Ni, Co, Cu, and Au and combinations thereof. 
   
   
       13 . The method of  claim 12  where said chemical metal deposition providing coating is a catalyst. 
   
   
       14 . In the fabrication of electrical apparatus where there are different circuitry entities the packaging method comprising the steps of:
 providing for positioning one circuitry entity on one surface of a supporting member of dielectric material and positioning different one of said entities on the remaining surface of said supporting member,
 providing said supporting member with a plurality of electrical pathways in an array arrangement between locations in said surfaces through said dielectric material,
 said plurality of electrical pathways through said dielectric material joining circuit locations in said circuitry entities, and,
 said electrical pathways through said dielectric material being filled with chemically deposited metal. 
 
 
   
   
   
       15 . The packaging method of  claim 14  here said metal is Ni. 
   
   
       16 . The packaging method of claim  17  wherein said chemical depositing of metal step involves the use of a catalyst.