Non-volatile memory devices including shared bit lines and methods of fabricating the same

Abstract

Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

1 . A non-volatile memory device having shared bit lines, comprising:
 a substrate;
 a field region on the substrate including a first field and a second field, the second field divided into sub regions via a bridge region; 
 an active region; and 
 a plurality of strings in the active region, the plurality of strings defined by the field region, with at least two of the strings connected via the active region in the bridge region. 
   
   
   
       2 . The non-volatile memory device of  claim 1 , further comprising:
 a bit line on the field region; and   a bit line contact that is a direct contact in the bridge region connecting the at least two strings to the bit line.   
   
   
       3 . The non-volatile memory device of  claim 2 , further comprising a plurality of word lines perpendicular to the field region and crossing above the active region and the field region. 
   
   
       4 . The non-volatile memory device of  claim 2 , further comprising:
 a plurality of field regions in parallel,   wherein the first fields and the second fields are alternately arranged,   the first fields and the second fields are longer in a first direction than a second direction perpendicular to the first direction, and   the plurality of strings are between the first fields and the second fields.   
   
   
       5 . The non-volatile memory device of  claim 4 , wherein the bridge regions are aligned one of horizontally and diagonally with respect to each other. 
   
   
       6 . The non-volatile memory device of  claim 2 , wherein the bit line contact extends to at least one of two adjacent sub regions. 
   
   
       7 . The non-volatile memory device of  claim 5 , wherein each of the bridge regions is convexly curved toward at least one of two adjacent first fields and two sub regions. 
   
   
       8 . The non-volatile memory device of  claim 7 , wherein the active region in each of the bridge regions is convexly curved toward at least one of two adjacent first fields and two sub regions. 
   
   
       9 . The non-volatile memory device of  claim 1 , wherein a tunneling oxide layer is on the active region. 
   
   
       10 . The non-volatile memory device of  claim 1 , wherein the field region includes an oxide layer, and
 the oxide of the field region is on the active region in each of the bridge regions.   
   
   
       11 . The non-volatile memory device of  claim 2 , wherein the bit line contact includes a barrier metal and a conductive material, and
 the bit lines are copper.   
   
   
       12 . The non-volatile memory device of  claim 11 , wherein the barrier metal is one of silicon nitride (SiN) spacer/titanium (Ti)/titanium nitride (TiN) and Ti/TiN, and
 the conductive material is one of tungsten and polysilicon.   
   
   
       13 . The non-volatile memory device of  claim 4 , wherein every two strings in the active region are connected via one of the bridge regions. 
   
   
       14 . A memory card comprising:
 the non-volatile memory device of  claim 1 ; and   a controller configured to control and exchange data with the non-volatile memory device.   
   
   
       15 . An electronic system comprising:
 the non-volatile memory device of  claim 1 ;   a processor configured to communicate with the non-volatile memory device via a bus; and   an input/output device configured to communicate via the bus.   
   
   
       16 - 26 . (canceled)