Patterning method and semiconductor device

Abstract

A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.

1 . A patterning method comprising:
 defining, in a case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions;   defining a second pattern by removing, in a case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern;   defining a third pattern by removing, in a case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and   using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.   
     
     
         2 . The patterning method according to  claim 1 , wherein a region which extends over a certain distance from a wiring for a control electrode arranged over the semiconductor substrate is selected as the first region. 
     
     
         3 . The patterning method according to  claim 1 , wherein a region which extends over a certain distance from a boundary between each first conduction type well region and the second conduction type well region arranged in the semiconductor substrate is selected as the first region. 
     
     
         4 . The patterning method according to  claim 1 , wherein a region which extends over a certain distance from at least one of an active region, a wiring layer, and an element arranged in the semiconductor substrate is selected as the first region. 
     
     
         5 . The patterning method according to  claim 1 , wherein a region which does not exceed a limit of patterning by a dry or wet wafer process is selected as the second region. 
     
     
         6 . The patterning method according to  claim 1 , wherein a region which does not exceed a limit of fabrication of a mask member used for patterning is selected as the second region. 
     
     
         7 . A semiconductor device wherein:
 in a case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern is defined between the first conduction type well regions;   a second pattern is defined by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; and   a third pattern defined by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern is arranged as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein the first conduction type well regions and the second conduction type well region make up a twin well structure. 
     
     
         9 . The semiconductor device according to  claim 7 , wherein the first conduction type well regions, the second conduction type well region, and another first or second conduction type well region make up a triple well structure.