Cmos device comprising mos transistors with recessed drain and source areas and non-conformal metal silicide regions

Abstract

A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used.

1 . A semiconductor device, comprising:
 a transistor comprising drain and source regions connecting to a channel region, at least one of said drain and source region having a recessed configuration and comprising a metal silicide layer having a non-conformal thickness; and   a strain-inducing dielectric layer that is in contact with said metal silicide layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein said metal silicide region has a first surface area and a second surface area that are substantially perpendicular to each other. 
   
   
       3 . The semiconductor device of  claim 2 , wherein a normal of said first surface area is oriented along a channel length direction. 
   
   
       4 . The semiconductor device of  claim 3 , wherein the thickness of said metal silicide in said first surface area is less than the thickness of said metal silicide in said second surface area. 
   
   
       5 . The semiconductor device of  claim 1 , wherein each of said drain and source regions comprises said recessed configuration and comprises said metal silicide with a non-conformal thickness. 
   
   
       6 . The semiconductor device of  claim 5 , wherein said non-conformal thickness in said drain region varies non-symmetrically relative to said non-conformal thickness of the metal silicide in the source region. 
   
   
       7 . The semiconductor device of  claim 5 , wherein each of said drain and source regions comprises said recessed configuration and wherein one of said drain and source regions comprises the metal silicide with a substantially conformal thickness. 
   
   
       8 . The semiconductor device of  claim 1 , wherein one of the drain region and the source region has a non-recessed configuration. 
   
   
       9 . The semiconductor device of  claim 1 , further comprising a second transistor comprising drain and source regions having a non-recessed configuration. 
   
   
       10 . The semiconductor device of  claim 1 , further comprising a second transistor having drain and source regions, wherein said second transistor is of opposite conductivity type compared to said transistor and wherein the drain and source regions of said second transistor have a recessed configuration. 
   
   
       11 . The semiconductor device of  claim 10 , wherein at least one of said drain and source regions of said second transistor comprises a metal silicide layer with a non-conformal thickness. 
   
   
       12 . A method, comprising:
 forming a recess in at least one of a drain region and a source region of a transistor;   forming a metal silicide layer in a non-conformal manner in said recess; and   forming a strain-inducing layer above said drain and source regions.   
   
   
       13 . The method of  claim 12 , wherein forming said metal silicide layer in a non-conformal manner comprises generating crystal damage in a non-conformal manner in said recess. 
   
   
       14 . The method of  claim 13 , wherein generating crystal damage comprises performing an ion implantation process. 
   
   
       15 . The method of  claim 14 , wherein said implantation process comprises an implantation using a non-zero tilt angle. 
   
   
       16 . The method of  claim 12 , wherein forming said metal silicide in a non-conformal manner comprises anisotropically depositing a metal and initiating a chemical reaction between said metal and a silicon material of the drain and source regions. 
   
   
       17 . The method of  claim 12 , wherein a recess is formed in said drain region and said source region and wherein said metal silicide is formed in a substantially conformal manner in one of said drain region and source region. 
   
   
       18 . The method of  claim 12 , wherein a recess is formed in said drain region and said source region and wherein said metal silicide is formed in a non-conformal manner in said drain region and said source region and wherein a degree of non-conformality is different in said drain and source regions. 
   
   
       19 . A method, comprising:
 forming a recess in at least one of a drain region and a source region of a transistor;   performing an ion implantation process to modify an exposed area of said at least one of a drain region and a source region in said recess in a non-conformal manner;   depositing a metal above said drain and source regions; and   performing a heat treatment to create a metal silicide in a non-conformal manner within said recess.   
   
   
       20 . The method of  claim 19 , further comprising forming a strain-inducing layer above said drain and source regions. 
   
   
       21 . The method of  claim 19 , wherein performing an ion implantation process comprises using a non-zero tilt angle. 
   
   
       22 . The method of  claim 19 , further comprising masking a second transistor prior to performing said implantation process. 
   
   
       23 . The method of  claim 22 , wherein said second transistor comprises a second recess in at least one of a drain region and a source region of said second transistor. 
   
   
       24 . The method of  claim 19 , wherein said recess is formed in the drain region and a further recess is formed in the source region and wherein said ion implantation is performed asymmetrically with respect to said drain and source regions. 
   
   
       25 . The method of  claim 22 , wherein said second transistor is a P-channel transistor and said transistor is an N-channel transistor.