Methods of Manufacturing Copper Interconnect Systems

Abstract

An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The allow seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region.

1 . An integrated circuit comprising:
 a substrate;   a first dielectric layer disposed over the substrate;   a first conductive region formed within a first trench in the first dielectric layer;   a metal-based cap layer disposed over the first conductive region, wherein the cap layer includes at least one of Cobalt, Boron, Tungsten, Phosphorous, or Ruthenium;   a second dielectric layer disposed over the first dielectric layer;   a first diffusion barrier disposed between the first and second dielectric layers; and   a second diffusion barrier disposed over horizontal surfaces of the second dielectric layer.   
     
     
         2 . The integrated circuit of  claim 1  wherein the first diffusion barrier is formed using at least one of the following materials: silicon nitride, Si—C, Si—C—N—O, Si—O—N, or Si—C—N. 
     
     
         3 . The integrated circuit of  claim 1 , further comprising a liner formed of at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta or other combinations thereof, or, an alloy or mixture comprising Ti added to Ta, Cr, Mo, W, Rh, Ru or Re. 
     
     
         4 . The integrated circuit of  claim 1  wherein the second diffusion barrier is a dielectric barrier formed using at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta or other combinations thereof, or, for adhesion enhancement, an alloy or mixture comprising Ti added to Ta, Cr, Mo, W, Rh, Ru or Re. 
     
     
         5 . The integrated circuit of  claim 1  wherein the second diffusion barrier is formed using at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta, or other combinations thereof, or an alloy or mixture comprising Ti added to Ta, Cr, Mo, W, Rh, Ru, or Re.