US2010001288A1PendingUtilityA1
Low Etch Pit Density (EPD) Semi-Insulating GaAs Wafers
Est. expiryMay 9, 2027(~0.8 yrs left)· nominal 20-yr term from priority
H10P 95/408C30B 11/00C30B 29/42C30B 33/02
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Abstract
A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.
Claims
exact text as granted — not AI-modified1 . A method for manufacture a gallium based material with a low etch pit density (EPD), the method comprising:
forming polycrystalline gallium based compounds; and performing vertical gradient freeze crystal growth using the polycrystalline gallium based compounds wherein the gallium based crystal has an etch pit density of less than 900 per square centimeter.
2 . The method of claim 1 , wherein the crystal has an etch pit density of about 600 per square centimeter.
3 . The method of claim 2 further comprising forming a gallium arsenide substrate from the gallium based crystal.
4 . The method of claim 2 further comprising forming a indium phosphide, gallium phosphide or other III-IV substrates from the gallium based crystal.
5 . The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a shape of the melt/crystal interface during the vertical gradient freeze crystal growth wherein the shape is concave or convex to a melt front.
6 . The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a crystallization velocity during the vertical gradient freeze crystal growth wherein the crystallization velocity is between 2 and 16 mm/hour.
7 . The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a temperature gradient at a melt/crystal interface during the vertical gradient freeze crystal growth wherein the temperature gradient at the melt/crystal interface is between 0.1 to 2 degrees Celsius.
8 . The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a total temperature gradient during the vertical gradient freeze crystal growth wherein the total temperature gradient is between 1 and 5 degrees Celsius.
9 . A method for manufacture a substrate with low light defects, the method comprising:
forming a gallium arsenide based substrate; annealing the gallium arsenide based substrate using a single step annealing; controlling the oxygen into a surface of the gallium based substrate during the annealing process; and removing a portion of the surface of the gallium based substrate to form a gallium arsenide based substrate having a predetermined oxygen content level and a light point defect of less than 1 per square centimeter per gallium arsenide based substrate with a particle size of greater than 0.3 micrometers.
10 . The method of claim 9 , wherein annealing the gallium arsenide based substrate further comprises controlling a heating rate during the annealing wherein the heating rate is 900 to 1050 degrees Celsius over 10 to 48 hours.
11 . The method of claim 9 , wherein annealing the gallium arsenide based substrate further comprises controlling a platform temperature during the annealing wherein the platform temperature is 900 to 1050 degrees Celsius.
12 . The method of claim 9 , wherein annealing the gallium arsenide based substrate further comprises controlling a cooling rate during the annealing wherein the cooling rate is to room temperature in 6 to 24 hours.
13 . A gallium based substrate, comprising:
a substrate having an etch pit density of less than 900 per square centimeter using a vertical gradient freeze process; and the substrate having less than 120 light point defects and a light point defect particle size of less than 0.3 micrometers.
14 . The substrate of claim 13 , wherein the substrate is gallium arsenide (GaAs).
15 . The substrate of claim 13 , wherein the substrate is indium phosphide, gallium phosphide or other III-V compounds.
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