Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench

Abstract

A method of forming a conductive trench such as a through-silicon-via in a silicon wafer is disclosed. The method includes depositing a mask over a wafer surface; patterning the mask to expose a portion of the wafer; exposing the wafer to a first etching step in which a first portion of the trench is formed; exposing the wafer to an second etching step in which a tapered second portion of the trench is formed, where the first portion has a continuously non-increasing width from the wafer surface to the second portion; and filling the trench with a conductive material. A silicon wafer including such a conductive trench is also disclosed.

1 . A method of forming a conductive trench in a silicon wafer, comprising:
 depositing a mask over a wafer surface;   patterning the mask to expose a portion of the wafer;   exposing the wafer to a first etching step in which a first portion of the trench is formed;   exposing the wafer to an second etching step in which a tapered second portion of the trench is formed, wherein the first portion has a continuously non-increasing width from the wafer surface to the second portion; and   filling the trench with a conductive material.   
   
   
       2 . The method according to  claim 1 , wherein the conductive trench is a via. 
   
   
       3 . The method according to  claim 1 , wherein the first etching step is an isotropic reactive ion etching step and the second etching step is an anisotropic reactive ion etching step. 
   
   
       4 . The method according to  claim 3 , wherein the isotropic etching step comprises a plurality of isotropic etching substeps. 
   
   
       5 . The method according to  claim 1 , further comprising depositing at least one layer selected from the group consisting of an insulating layer and a seed layer in the trench prior to filling the trench with the conductive material. 
   
   
       6 . The method according to  claim 1 , wherein the conductive material is selected from the group consisting of copper, titanium and aluminum. 
   
   
       7 . The method according to  claim 1 , further comprising exposing the first trench portion to a passivation step between the first etching step and the second etching step. 
   
   
       8 . The method according to  claim 3 , wherein the isotropic etching step comprises exposing the portion of the wafer to a mixture of SF 6  and O 2 . 
   
   
       9 . The method according to  claim 3 , wherein the anisotropic reactive ion etching step comprises exposing the portion of the wafer to a mixture of SF 6 , O 2  and C 4 F 8 . 
   
   
       10 . The method according to  claim 2 , wherein the via is a blind via, the method further comprising thinning the wafer to expose the blind via. 
   
   
       11 . A silicon wafer comprising a conductive trench, the conductive trench comprising:
 a first portion; and   a second portion having a tapered shape, wherein the first portion has a different shape than the second portion, and has a continuously non-increasing width from a wafer surface to the second portion.   
   
   
       12 . The silicon wafer according to  claim 11 , wherein the conductive trench is a via extending through the silicon wafer. 
   
   
       13 . The semiconductor body or a silicon wafer according to  claim 11 , further comprising an insulating layer between the conductive trench and the silicon wafer. 
   
   
       14 . A device comprising:
 a silicon wafer including a via extending through the silicon wafer, wherein the via includes a first portion and a second portion having a tapered shape, wherein the first portion has a different shape than the second portion, and has a continuously non-increasing width from a wafer surface to the second portion;   a first semiconductor device mounted on a first surface of the silicon wafer; and   a second semiconductor device mounted on an opposite surface of the silicon wafer, the first semiconductor device and the second semiconductor device being conductively connected through the via.   
   
   
       15 . The device according to  claim 14 , wherein the silicon wafer, the first semiconductor device and the second semiconductor device are part of a system in package.