US2010019362A1PendingUtilityA1

Isolated stacked die semiconductor packages

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Assignee: GALERA MANOLITOPriority: Jul 23, 2008Filed: Jul 23, 2008Published: Jan 28, 2010
Est. expiryJul 23, 2028(~2 yrs left)· nominal 20-yr term from priority
H10W 90/726H10W 90/811H10W 70/453H10W 70/442H10W 70/421H10W 70/415
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Claims

Abstract

Semiconductor packages that contain isolated stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using differing arrays of metal strips that serve as interposers between the first and second dies. This configuration provides a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.

Claims

exact text as granted — not AI-modified
1 . A semiconductor package, comprising:
 multiple land pads;   a first die connected to a first portion of the lands pads without wirebonding;   an array of connectors connected to a second portion of the land pads; and   a second die connected to the array of connectors without wirebonding, wherein the second die is isolated from the first die.   
   
   
       2 . The semiconductor package of  claim 1 , wherein the first die contains a first integrated circuit device and the second die contains a second integrated circuit device. 
   
   
       3 . The semiconductor package of  claim 1 , wherein the second die does not contact the first die. 
   
   
       4 . The semiconductor package of  claim 3 , wherein the semiconductor package has a thickness less than about 1 mm. 
   
   
       5 . The semiconductor package of  claim 4 , wherein the semiconductor package has a thickness ranging from about 0.8 mm to about 1 mm. 
   
   
       6 . The semiconductor package of  claim 1 , wherein the first die is smaller than the second die and the connectors are substantially columnar in shape. 
   
   
       7 . The semiconductor package of  claim 1 , wherein the first die is substantially the same size or smaller than the second die and the connectors contain a first portion extending away from the landing pads and a second portion extending towards the second die. 
   
   
       8 . The semiconductor package of  claim 1 , further comprising a molding material encapsulating the connectors and the first and second dies. 
   
   
       9 . The semiconductor package of  claim 1 , wherein the multiple land pads terminate in terminals for the package. 
   
   
       10 . A semiconductor package, comprising:
 multiple land pads;   a first die containing a first integrated circuit device and connected to a first portion of the lands pads without wirebonding;   an array of connectors connected to a second portion of the land pads; and   a second die containing a second integrated circuit device and connected to the array of connectors without wirebonding, wherein the second die is isolated from the first die and does not contact the first die.   
   
   
       11 . The semiconductor package of  claim 10 , wherein the semiconductor package has a thickness less than about 1 mm. 
   
   
       12 . The semiconductor package of  claim 11 , wherein the semiconductor package has a thickness ranging from about 0.8 mm to about 1 mm. 
   
   
       13 . The semiconductor package of  claim 10 , wherein the first die is smaller than the second die and the connectors are substantially columnar in shape. 
   
   
       14 . The semiconductor package of  claim 10 , wherein the first die is substantially the same size or smaller than the second die and the connectors contain a first portion extending away from the landing pads and a second portion extending towards the second die. 
   
   
       15 . The semiconductor package of  claim 10 , further comprising a molding material encapsulating the connectors and the first and second dies. 
   
   
       16 . The semiconductor package of  claim 10 , wherein the multiple land pads terminate in terminals for the package. 
   
   
       17 . A method for making semiconductor package, comprising:
 providing multiple land pads;   connecting a first die to a first portion of the lands pads without using wirebonding;   connecting an array of connectors to a second portion of the land pads; and   connecting a second die to the array of connectors without using wirebonding and without contacting the second die to the first die.   
   
   
       18 . The method of  claim 17 , further including providing the semiconductor package with a thickness less than about 1 mm. 
   
   
       19 . The method of  claim 18 , wherein the semiconductor package has a thickness ranging from about 0.8 mm to about 1 mm. 
   
   
       20 . The method of  claim 17 , wherein the first die is smaller than the second die and the connectors are substantially columnar in shape. 
   
   
       21 . The method of  claim 17 , wherein the first die is substantially the same size or smaller than the second die and the connectors contain a first portion extending away from the landing pads and a second portion extending towards the second die. 
   
   
       22 . The method of  claim 1 , further comprising encapsulating a molding material around the connectors and the first and second dies. 
   
   
       23 . A method for making semiconductor package having a thickness less than about 1 mm, comprising:
 providing a substrate;   forming multiple land pads on the substrate by a deposition and etch procedure;   connecting a first die to an inner portion of the lands pads by using a flip chip procedure without using wirebonding;   connecting an array of connectors to an outer portion of the land pads;   connecting a second die to the array of connectors by using a flip chip procedure without using wirebonding, wherein the second die rests on the connectors without contacting the first die;   encapsulating a molding material around the connectors and the first and second dies without underfilling; and   removing the substrate.   
   
   
       24 . The method of  claim 23 , wherein the first die is smaller than the second die and the connectors are substantially columnar in shape. 
   
   
       25 . The method of  claim 23 , wherein the first die is substantially the same size or smaller than the second die and the connectors contain a first portion extending away from the landing pads and a second portion extending towards the second die.

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