Inventor · disambiguated record
Manolito Galera
Also filed as: GALERA MANOLITO · GALERA MANOLITO FABRES
11 granted patents·7 pending applications·46 citations·filing 2008–2011
88Inventor score
Top patents by PatentIndex Score
18 records- 0186US8053883B2Isolated stacked die semiconductor packagesFAIRCHILD SEMICONDUCTOR·Filed 2010·Granted Nov 8, 2011·7 cites·20 claims
- 0281US7846773B2Multi-chip semiconductor packageFAIRCHILD SEMICONDUCTOR·Filed 2009·Granted Dec 7, 2010·9 cites·16 claims
- 0374US7923847B2Semiconductor system-in-a-package containing micro-layered lead frameFAIRCHILD SEMICONDUCTOR·Filed 2008·Granted Apr 12, 2011·6 cites·25 claims
- 0471US7960211B2Semiconductor system-in-package and method for making the sameFAIRCHILD SEMICONDUCTOR·Filed 2008·Granted Jun 14, 2011·4 cites·24 claims
- 0569US7888781B2Micro-layered lead frame semiconductor packagesFAIRCHILD SEMICONDUCTOR·Filed 2008·Granted Feb 15, 2011·4 cites·20 claims
- 0668US8314480B2Stackable semiconductor package with embedded die in pre-molded carrier frameGALERA MANOLITO FABRES·Filed 2010·Granted Nov 20, 2012·4 cites·20 claims
- 0768US8198132B2Isolated stacked die semiconductor packagesGALERA MANOLITO·Filed 2011·Granted Jun 12, 2012·2 cites·20 claims
- 0865US7977776B2Multichip discrete packageFAIRCHILD SEMICONDUCTOR·Filed 2009·Granted Jul 12, 2011·3 cites·18 claims
- 0965US7843048B2Multi-chip discrete devices in semiconductor packagesFAIRCHILD SEMICONDUCTOR·Filed 2008·Granted Nov 30, 2010·3 cites·25 claims
- 1062US7944031B2Leadframe-based chip scale semiconductor packagesFAIRCHILD SEMICONDUCTOR·Filed 2008·Granted May 17, 2011·2 cites·25 claims
- 1159US8072051B2Folded lands and vias for multichip semiconductor packagesGALERA MANOLITO·Filed 2009·Granted Dec 6, 2011·2 cites·24 claims
- 1249US2010019362A1Isolated stacked die semiconductor packagesGALERA MANOLITO·Filed 2008·Application pending·0 cites
- 1344US2010276793A1High pin density semiconductor system-in-a-packageGALERA MANOLITO·Filed 2009·Application pending·0 cites
- 1443US2010127380A1Leadframe free leadless array semiconductor packagesGALERA MANOLITO·Filed 2008·Application pending·0 cites
- 1543US2010127375A1Wafer level chip scale semiconductor packagesGALERA MANOLITO·Filed 2008·Application pending·0 cites
- 1642US2010308461A1Multi-chip semiconductor packageGALERA MANOLITO·Filed 2010·Application pending·0 cites
- 1740US2010140773A1Stacked chip, micro-layered lead frame semiconductor packageGALERA MANOLITO FABRES·Filed 2008·Application pending·0 cites
- 1830US2011163428A1Semiconductor packages with embedded heat sinkGALERA MANOLITO FABRES·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →