Multi-chip semiconductor package

Abstract

Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.

1 . A semiconductor package, comprising:
 a land pad array comprising an inner portion, a middle portion, and an outer portion, the middle and outer portions having solders balls thereon;   a first die containing an integrated circuit device connected to the inner portion of the land pad array;   a second die containing an integrated circuit device disposed over the first die and resting on first routing leads that are connected to the solder balls on the middle portion of the land pad array;   a third die containing an integrated circuit device disposed on the backside of the second die and connected to second routing leads that are connected to the solder balls on the outer portion of the land pad array; and   a molding material.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the lands of the land pad array are not physically connected to each other. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the molding material comprises a first portion partially encapsulating the first die and the solder balls except for an upper surface of the solder balls. 
     
     
         4 . The semiconductor package of  claim 3 , wherein the molding material comprises a second portion encapsulating the routing leads, the second die, and the third die. 
     
     
         5 . The semiconductor package of  claim 4 , wherein the first portion and the second portion of the molding material are formed separately. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the first die is connected to the inner portion of the land pad array by wirebonds. 
     
     
         7 . The semiconductor package of  claim 1 , wherein the first routing leads extend from the solder balls on the middle portion towards the interior of the package over the first die. 
     
     
         8 . The semiconductor package of  claim 1 , wherein the third die is connected to the second routing leads by wirebonds. 
     
     
         9 . An electronic device containing a semiconductor package, the package comprising:
 a land pad array comprising an inner portion, a middle portion, and an outer portion, the middle and outer portions having solders balls thereon;   a first die containing an integrated circuit device connected to the inner portion of the land pad array;   a second die containing an integrated circuit device disposed over the first die and resting on first routing leads that are connected to the solder balls on the middle portion of the land pad array;   a third die containing an integrated circuit device disposed on the backside of the second die and connected to second routing leads that are connected to the solder balls on the outer portion of the land pad array; and   a molding material.   
     
     
         10 . The electronic device of  claim 9 , wherein the lands of the land pad array are not physically connected to each other. 
     
     
         11 . The electronic device of  claim 9 , wherein the molding material comprises a first portion partially encapsulating the first die and the solder balls except for an upper surface of the solder balls. 
     
     
         12 . The electronic device of  claim 11 , wherein the molding material comprises a second portion encapsulating the routing leads, the second die, and the third die. 
     
     
         13 . The electronic device of  claim 12 , wherein the first portion and the second portion of the molding material are formed separately. 
     
     
         14 . The electronic device of  claim 9 , wherein the first die is connected to the inner portion of the land pad array by wirebonds. 
     
     
         15 . The electronic device of  claim 9 , wherein the first routing leads extend from the solder balls on the middle portion towards the interior of the package over the first die. 
     
     
         16 . The electronic device of  claim 9 , wherein the third die is connected to the second routing leads by wirebonds. 
     
     
         17 . The electronic device of  claim 9 , further comprising a circuit board connected to the land pad array through solder bumps or balls. 
     
     
         18 . A method for making semiconductor package, comprising:
 providing a land pad array comprising an inner portion, a middle portion, and an outer portion, the middle and outer portions having solders balls thereon;   providing a first die containing an integrated circuit device connected to the inner portion of the land pad array;   providing a second die containing an integrated circuit device disposed over the first die and resting on first routing leads that are connected to the solder balls on the middle portion of the land pad array;   providing a third die containing an integrated circuit device disposed on the backside of the second die and connected to second routing leads that are connected to the solder balls on the outer portion of the land pad array; and   providing a molding material.   
     
     
         19 . (canceled) 
     
     
         20 . (canceled) 
     
     
         21 . (canceled) 
     
     
         22 . (canceled) 
     
     
         23 . (canceled) 
     
     
         24 . (canceled) 
     
     
         25 . (canceled) 
     
     
         26 . The method of  claim 18 , wherein the lands of the land pad array are not physically connected to each other. 
     
     
         27 . The method of  claim 18 , wherein the molding material comprises a first portion partially encapsulating the first die and the solder balls except for an upper surface of the solder balls. 
     
     
         28 . The method of  claim 27 , wherein the molding material comprises a second portion encapsulating the first and second routing leads, the second die, and the third die. 
     
     
         29 . The method of  claim 28 , wherein the first portion and the second portion of the molding material are formed separately. 
     
     
         30 . A method for making semiconductor package, comprising:
 forming an interconnect structure comprising an inner portion, a middle portion, and an outer portion;   forming solder balls on the middle and outer potions of the interconnect structure;   connecting a first die containing an integrated circuit device to the inner portion of the interconnect structure;   providing a first molding material around the first die and the solder balls except for an upper surface of the solder balls;   forming first routing leads from an inner portion of the solder balls to a location over the first die;   forming second routing leads;   attaching a second die containing an integrated circuit device to the first routing leads;   connecting a third die containing an integrated circuit device to the second routing leads; and   forming a second molding material to encapsulate the first and second routing leads, the second die, and the third die.   
     
     
         31 . The method of  claim 30 , wherein the lands of the land pad array are not physically connected to each other. 
     
     
         32 . The method of  claim 30 , wherein the molding material comprises a first portion partially encapsulating the first die and the solder balls except for an upper surface of the solder balls. 
     
     
         33 . The method of  claim 32 , wherein the molding material comprises a second portion encapsulating the first and second routing leads, the second die, and the third die. 
     
     
         34 . The method of  claim 33 , wherein the first portion and the second portion of the molding material are formed separately.