Semiconductor device package and method of fabricating the same

Abstract

A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

1 . A semiconductor device package comprising:
 a semiconductor chip including a conductive pad;   a die pad including a top surface on which the semiconductor chip is mounted and a bottom surface opposing the top surface, the die pad having a first thickness between the top surface and the bottom surface;   a lead pattern including a first portion contiguously disposed at the edge of the die pad and having the first thickness and a second portion merged with the first portion and having a second thickness greater than the first thickness;   a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface facing the die pad and the lead pattern; and   a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.   
   
   
       2 . The semiconductor device package of  claim 1 , wherein the heat radiation member includes an edge portion formed at its edge and having a third thickness and a groove formed at an inner side of the edge portion and having a fourth depth. 
   
   
       3 . The semiconductor device package of  claim 1 , wherein a bottom surface of the lead pattern is coplanar with a bottom surface of the die pad. 
   
   
       4 . The semiconductor device package of  claim 2 , wherein the second portion of the lead pattern is in contact with the edge portion of the heat radiation member. 
   
   
       5 . The semiconductor device package of  claim 2 , wherein the groove is defined by inner side surfaces of the edge portion and a plane connecting the inner side surfaces to each other. 
   
   
       6 . The semiconductor device package of  claim 5 , wherein the conductive line is disposed at a space defined by the plane, a top surface of the first portion of the lead pattern, and a top surface of the die pad. 
   
   
       7 . The semiconductor device package of  claim 5 , wherein the conductive line includes a first portion that is curved and inserted into the groove and a second portion that is not inserted into the groove. 
   
   
       8 . The semiconductor device package of  claim 5 , further comprising:
 an insulating layer disposed to cover the inner side surfaces and the plane of the groove.   
   
   
       9 . The semiconductor device package of  claim 1 , wherein the heat radiation member includes an edge portion disposed at its edge and having the third thickness, a central portion aligned to the mounted semiconductor chip and having the third thickness, and a groove formed between the edge portion and the central portion and having a fourth depth that is smaller than the third thickness. 
   
   
       10 . The semiconductor device package of  claim 1 , wherein a plurality of grooves are formed at the heat radiation member to correspond to the conductive lines, respectively, the grooves each having a fourth depth. 
   
   
       11 . The semiconductor device package of  claim 1 , further comprising a molding part. 
   
   
       12 . The semiconductor device package of  claim 1  is an exposed lead package. 
   
   
       13 . The semiconductor device package of  claim 1 , wherein the bottom surface of the die pad is exposed and connected to a ground. 
   
   
       14 . The semiconductor device package of  claim 1 , further comprising an adhesive layer disposed between the semiconductor chip and the die pad. 
   
   
       15 . The semiconductor device package of  claim 14 , wherein the adhesive layer is an epoxy-based or silicon-based adhesive of a liquid or film type. 
   
   
       16 . The semiconductor device package of  claim 1 , further comprising a plating layer disposed on a top surface of the first portion of the lead pattern. 
   
   
       17 . The semiconductor device package of  claim 17 , wherein the plating layer comprises silver or palladium. 
   
   
       18 . A semiconductor device package, comprising:
 a conductive plate patterned into a lead pattern and a die pad spaced apart from each other, the lead pattern disposed at an edge of the die pad and including a first portion having a same thickness as and adjacent to the die pad and a second portion having a thickness greater than the thickness of the first portion, the first portion being disposed between the second portion and the die pad;   a semiconductor chip including at least one conductive pad and disposed on the die pad;   a heat radiation member including opposing ends disposed on the second portions of the lead pattern and including a groove formed at its bottom surface facing the die pad and the first portion of the lead pattern; and   a conductive line disposed to electrically connect the at least one conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.   
   
   
       19 - 27 . (canceled)