Annealing method for semiconductor device with silicon carbide substrate and semiconductor device

Abstract

In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H 2 O to be not larger than 10 −2 Pa, preferably not larger than 10 −3 Pa, surface irregularity of the silicon carbide (SiC) substrate is controlled to be not greater than 2 nm, more preferably not greater than 1 nm in RMS value.

1 . An annealing method for annealing a device including a silicon carbide substrate, the method comprising steps of:
 forming an impurity doped region in the silicon carbide substrate by ion-implantation of the impurity into the silicon carbide substrate; and   annealing the impurity doped region in the silicon carbide substrate,   wherein a partial pressure of H 2 O in an annealing atmosphere during the annealing step is not larger than 10 −2  Pa.   
     
     
         2 . The annealing method according to  claim 1 , wherein
 the silicon carbide substrate includes an epitaxial silicon carbide crystalline layer as a surface layer, and   the impurity doped region is formed in the silicon carbide crystalline layer.   
     
     
         3 . The annealing method according to  claim 1 , wherein, during the annealing step, the partial pressure of H 2 O is controlled to be not larger than 10 −3  Pa. 
     
     
         4 . The annealing method according to  claim 1 , wherein, during the annealing step, the silicon carbide substrate implanted with the impurity is covered by a cap having a through-hole. 
     
     
         5 . The annealing method according to  claim 1 , wherein the annealing step is carried out in a vacuum vessel that is evacuated of air so that a pressure in the vacuum vessel is not greater than 10 −4  Pa. 
     
     
         6 . A semiconductor device comprising:
 a silicon carbide substrate; and   an impurity doped region in the substrate,   wherein the impurity doped region is annealed in an annealing atmosphere in which a partial pressure of H 2 O is not larger than 10 −2  Pa, so that a surface flatness of the silicon carbide substrate is not greater than 2 nm in RMS value.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the semiconductor device includes a P-N junction. 
     
     
         8 . A semiconductor device according to  claim 6 , wherein the surface flatness of the silicon carbide substrate is not greater than 1 nm in RMS value.