Nonvolatile memory device and methods of forming the same

Abstract

Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

1 . A nonvolatile memory device comprising:
 device isolation layers formed in a substrate to define an active region between the device isolation layers;   first and second impurity regions separately formed in the active region to define a channel region therebetween;   a middle gate formed on the channel region;   a gate insulating layer adjacent to sidewalls and a bottom of the middle gate;   first and second memory cells adjacent to the sidewalls of the middle gate and spaced apart from each other, the first and second memory cells each including a memory layer on the channel region and a side gate formed on the memory layer;   a first spacer layer covering outer sides of the memory layer and the side gate; and   a second spacer layer covering the first spacer layer,   wherein each of the first and second impurity regions include a low concentration impurity region formed under the second spacer layer and a high concentration impurity region self-aligned to the second spacer layer.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein the memory layer includes a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer on the channel region. 
     
     
         3 . The nonvolatile memory device of  claim 2 , wherein the charge storage layer is formed of a single material. 
     
     
         4 . The nonvolatile memory device of  claim 2 , wherein the charge storage layer is formed of amorphous silicon. 
     
     
         5 . The nonvolatile memory device of  claim 1 , further comprising:
 a gate connection layer formed on the middle gate and the side gates to electrically connect the middle gate with the side gates.   
     
     
         6 . The nonvolatile memory device of  claim 1 , wherein the first spacer layers is formed of silicon oxide and the second spacer layer is formed of silicon nitride. 
     
     
         7 . The nonvolatile memory device of  claim 1 , wherein the middle gate and the side gate cross the device isolation layers and the memory layer is disposed between sidewalls of the device isolation layers. 
     
     
         8 . The nonvolatile memory device of  claim 1 , wherein a top surface of the memory layer is coplanar with a top surface of the device isolation layers. 
     
     
         9 . A nonvolatile memory device comprising:
 device isolation layers formed in a substrate to define an active region between the device isolation layers;   a middle gate crossing the active region;   a gate insulating layer adjacent to sidewalls and a bottom of the middle gate;   first and second memory cells adjacent to the sidewalls of the middle gate and spaced apart from each other, the first and second memory cells each including a side gate crossing the active region and a memory layer between the side gate and the active region,   wherein the memory layer is disposed between sidewalls of the device isolation layers.   
     
     
         10 . The nonvolatile memory device of  claim 9 , wherein a top surface of the memory layer is coplanar with a top surface of the device isolation layers. 
     
     
         11 . The nonvolatile memory device of  claim 9 , wherein the memory layer includes a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer on the channel region. 
     
     
         12 . The nonvolatile memory device of  claim 11 , wherein the charge storage layer is formed of a single material. 
     
     
         13 . The nonvolatile memory device of  claim 11 , wherein the charge storage layer is formed of a single material. 
     
     
         14 . The nonvolatile memory device of  claim 9 , further comprising:
 a gate connection layer formed on the middle gate and the side gates to electrically connect the middle gate with the side gates.   
     
     
         15 . The nonvolatile memory device of  claim 9 , further comprising:
 a first spacer layer covering outer sides of the first and second memory cells.   
     
     
         16 . The nonvolatile memory device of  claim 15 , further comprising:
 a second spacer layer covering the first spacer layer, wherein each of the first and second impurity regions include a low concentration impurity region formed under the second spacer layer and a high concentration impurity region self-aligned to the second spacer layer.