Semiconductor wafer with adhesive protection layer

Abstract

A semiconductor wafer with an adhesive protection layer includes: a wafer body having a first surface and an opposing second surface; a plurality of electrical connection pads formed on the second surface of the wafer body; and the adhesive protection layer formed on the second surface of the wafer body and the plurality of electrical connection pads, wherein the protection layer is made of a material including a photosensitive adhesive, a thermal-setting adhesive and a dielectric material. The protection layer not only isolates circuits on the wafer surface from external moisture and contaminant, but also can be patterned and is adhesive, such that the wafer can be mounted to a circuit substrate in a subsequent process by the protection layer, without having to apply an additional adhesive on the wafer, thereby greatly simplifying the wafer-substrate attachment procedure during package fabrication processes.

1 . A semiconductor wafer with an adhesive protection layer, comprising:
 a wafer body having a first surface and an opposing second surface;   a plurality of electrical connection pads formed on the second surface of the wafer body; and   the adhesive protection layer formed on the second surface of the wafer body and the plurality of electrical connection pads, wherein the protection layer is made of a material comprising a photosensitive adhesive, a thermal-setting adhesive and a dielectric material, and allows the semiconductor wafer being singulated to be mounted to a package carrier.   
     
     
         2 . The semiconductor wafer of  claim 1 , wherein the first surface of the wafer body is an inactive surface and the second surface of the wafer body is an active surface formed with predetermined circuit layouts thereon. 
     
     
         3 . The semiconductor wafer of  claim 1 , wherein each of the first and second surfaces of the wafer body is an active surface formed with predetermined circuit layouts thereon. 
     
     
         4 . The semiconductor wafer of  claim 3 , further comprising: a plurality of electrical connection pads formed on the first surface of the wafer body; and another adhesive protection layer formed on the first surface of the wafer body and the plurality of electrical connection pads. 
     
     
         5 . The semiconductor wafer of  claim 1 , wherein the protection layer further comprises a plurality of openings where at least a part of each of the electrical connection pads is exposed. 
     
     
         6 . The semiconductor wafer of  claim 1 , wherein the protection layer further comprises at least an opening where all the electrical connection pads are exposed. 
     
     
         7 . The semiconductor wafer of  claim 6 , wherein the opening of the protection layer exposes top surfaces and side surfaces of the electrical connection pads. 
     
     
         8 . The semiconductor wafer of  claim 1 , which is a silicon wafer or an AsGa wafer. 
     
     
         9 . The semiconductor wafer of  claim 1 , wherein the electrical connection pads are made of aluminum or copper. 
     
     
         10 . The semiconductor wafer of  claim 1 , wherein the dielectric material is polyimide, silicon dioxide, silicon nitride, or a combination thereof. 
     
     
         11 . The semiconductor wafer of  claim 5 , further comprising: a plurality of conductive bumps formed on the electrical connection pads respectively. 
     
     
         12 . The semiconductor wafer of  claim 7 , further comprising: a plurality of conductive bumps formed on the electrical connection pads respectively and covering the side surfaces of the electrical connection pads. 
     
     
         13 . The semiconductor wafer of  claim 5 , wherein the photosensitive adhesive of the protection layer is a cured photosensitive adhesive. 
     
     
         14 . The semiconductor wafer of  claim 1 , further comprising: a removable cover layer disposed on the protection layer. 
     
     
         15 . The semiconductor wafer of  claim 11 , wherein the conductive bumps are made of aluminum, copper, titanium, tin, lead, gold, bismuth, zinc, nickel, zirconium, magnesium, indium, antinomy, tellurium, or a combination thereof.