Disabling portions of memory with defects

Abstract

An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.

1 . A method comprising:
 tracking a number of errors associated with a cache location of a cache memory within a processor;   determining if the cache location includes a defect based on the number of errors;   determining if it is allowable to disable the cache location; and   disabling the cache location in response to determining the cache location includes a defect and determining it is allowable to disable the cache location.   
     
     
         2 . The method of  claim 1  wherein tracking a number of errors associated with a cache location comprises tracking the number of errors associated with the cache location from a reset event for the processor. 
     
     
         3 . The method of  claim 2  wherein tracking the number of errors associated with the cache location from a rest event for the processor comprises tracking the number of errors associated with the cache location from the reset event in a hardware table within the processor, the hardware table to hold addressing information for the cache location associated with a count for the number of errors associated with the cache location. 
     
     
         4 . The method of  claim 2  wherein determining if the cache location includes a defect based on the number of errors comprises determining if the number of errors associated with the cache location from the reset event has reached an upper limit of errors, and determining the cache location includes the defect in response to determining the number of errors has reached the upper limit. 
     
     
         5 . The method of  claim 4  wherein the upper limit is to be specified by hardware. 
     
     
         6 . The method of  claim 4  wherein the upper limit is to be specified by software. 
     
     
         7 . The method of  claim 2  wherein determining if it is allowable to disable the cache location comprises determining an amount of cache locations disabled, determine if the amount of cache locations disabled has reached a limit of cache locations capable of being disabled, and determining it is allowable to disable the cache location in response to determining the amount of cache locations disabled has not reached the limit of cache locations capable of being disabled. 
     
     
         8 . The method of  claim 7  wherein the cache location includes a way within a set of the cache, and wherein the limit of cache locations capable of being disabled is half of a number of ways within the set. 
     
     
         9 . The method of  claim 8  further comprising not disabling the way within the set of the cache in response to determining it is not allowable to disable the cache location responsive to determining the amount of ways within the set disabled has reached the limit of half of the number of ways within the set. 
     
     
         10 . The method of  claim 1  further comprising flushing the cache location before disabling the cache location in response to determining the cache location includes the defect and determining it is allowable to disable the cache location, and wherein disabling the cache location comprises restricting future accesses to the cache location. 
     
     
         11 . An apparatus comprising:
 an error detection module to detect a first error upon a first access to a cache location within a cache memory of a processor and a subsequent error upon a subsequent access to the cache location, the first and subsequent accesses being separated by a plurality of accesses to the cache location that do not exhibit errors;   an error tracking module coupled to the error detection module to track a continuous count of errors including the first error and the subsequent error associated with the cache location from a reset event of the processor;   a defect determination module coupled to the error tracking module to determine the cache location includes a defect in response to the continuous count of errors reaching a limit of errors; and   a memory control module coupled to the defect determination module to disable the cache location in response to the defect determination module determining the cache location includes a defect.   
     
     
         12 . The apparatus of  claim 11  wherein the memory control module is further to move data held in the cache location before disabling the cache location in response to the defect determination module determining the cache location includes a defect. 
     
     
         13 . The apparatus of  claim 12  wherein the memory control module to move data held in the cache location comprises the memory control module to move data held in the cache location to a higher level memory location associated with the cache location. 
     
     
         14 . The apparatus of  claim 12  wherein the memory control module to move data held in the cache location comprises the memory control module to move data held in the cache location to replacement location within the cache memory. 
     
     
         15 . The apparatus of  claim 11  wherein the memory control module is further to flush the cache location before disabling the cache location. 
     
     
         16 . The apparatus of  claim 11  wherein the error tracking module is to restart the continuous count of errors upon the reset event of the processor. 
     
     
         17 . The apparatus of  claim 11  wherein the error detection module to detect the first error and the subsequent error includes hardware to receive Error Correction Code (ECC) signals to indicate the first error was detected upon the first access to the cache location and the subsequent error was detected upon the subsequent access to the cache location. 
     
     
         18 . The apparatus of  claim 11  wherein the defect determination module is further to determine if it is allowable to disable the cache location in response to the continuous count of errors reaching the limit of errors, and wherein memory control module to disable the cache location in response to the defect determination module determining the cache location includes a defect is further responsive to the defect determination module determining it is allowable to disable the cache location. 
     
     
         19 . The apparatus of  claim 18  wherein the defect determination module to determine if it is allowable to disable the cache location comprises the defect determination module to:
 determine if a number of currently disabled cache locations has reached a limit of cache locations capable of being disabled in the cache memory,   determine it is allowable to disable the cache location in response to determining the number of currently disabled cache locations has not reached the limit of cache locations capable of being disabled in the cache memory, and   determine it is not allowable to disable the cache location in response to determining the number of currently disabled cache locations has reached the limit of cache locations capable of being disabled in the cache memory.   
     
     
         20 . The system of  claim 19 , wherein the limit of cache locations capable of being disabled in the cache memory is defined by hardware, and wherein the limit of errors is defined by software. 
     
     
         21 . An article of manufacture comprising program code which, when executed by a machine, causes the machine to perform the operations of:
 receiving error detection information for a cache in a processor of the machine from error detection logic in the processor;   tracking, in a software data structure, errors associated with a portion of the cache over time based on the error detection information received from the error detection logic;   determining if the portion of the cache is defective based on the errors associated with the portion of cache tracked in the software data structure and an upper limit of errors;   initiating a disable operation, when executed by the processor of the machine, to disable the portion of the cache conditioned upon determining the portion of the cache is defective.   
     
     
         22 . The article of manufacture of  claim 21 , wherein determining if the portion of the cache is defective based on the errors associated with the portion of cache tracked in the software data structure and an upper limit of errors comprises determining the portion of cache is defective in response to the errors associated with the portion of cache reaching the upper limit. 
     
     
         23 . The article of manufacture of  claim 22 , wherein the portion of the cache includes a cache line of the cache. 
     
     
         24 . The article of manufacture of  claim 23 , wherein the disable operation includes a disable instruction, and wherein initiating the disable instruction, when executed by the processor of the machine, to disable the cache line conditioned upon determining the cache line is defective comprises: the processor executing the disable instruction to update a bit corresponding to the cache line to indicate the cache line is defective conditioned upon determining the cache line is defective. 
     
     
         25 . The article of manufacture of  claim 23 , wherein the program code which, when executed by a machine, further causes the machine to perform the operations of: determining if it is allowable to disable the cache line, and wherein initiating the disable operation, when executed by the processor of the machine, to disable the cache line is further conditioned upon determining it is allowable to disable the cache line. 
     
     
         26 . The article of manufacture of  claim 25  wherein determining if it is allowable to disable the cache line comprises: determining if a limit of disabled cache lines within a set including the cache line has been reached, and determining it is allowable to disable the cache line if the limit of disabled cache lines within the set including the cache line has not been reached. 
     
     
         27 . The article of manufacture of  claim 21  wherein tracking, in a software data structure, errors associated with a portion of the cache over time based on the error detection information received from the error detection logic; comprises keeping a cumulative count of a number of errors associated with the portion of the cache over time from a reset event of the machine. 
     
     
         28 . The article of manufacture of  claim 27 , wherein the error detection logic comprises Error Correction Code (ECC) logic.