Mask ROM and method of fabricating the same

Abstract

A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

1 . A mask read-only memory (ROM) comprising:
 a dielectric layer formed on a substrate;   a plurality of first conductive lines formed on the dielectric layer;   a plurality of diodes formed in the first conductive lines;   a plurality of final vias formed for a first set of the diodes each representing a first type of memory cell, wherein no final via is formed for a second set of diodes each representing a second type of memory cell; and   a plurality of second conductive lines, each formed over a column of the diodes.   
   
   
       2 . The mask ROM of  claim 1 , wherein the final vias are formed under a top-most interconnect layer. 
   
   
       3 . The mask ROM of  claim 2 , wherein the second conductive lines are formed as the top-most interconnect layer. 
   
   
       4 . The mask ROM of  claim 1 , wherein the second conductive lines used as bit-lines are formed perpendicular to the first conductive lines used as word lines with each of the diodes being formed at an intersection of the first and second conductive lines. 
   
   
       5 . The mask ROM of  claim 1 , wherein each final via couples a respective one of the diodes to a respective one of the second conductive lines. 
   
   
       6 . The mask ROM of  claim 1 , wherein the dielectric layer covers an integrated circuit formed on the semiconductor substrate. 
   
   
       7 . The mask ROM of  claim 1 , wherein the first conductive lines are comprised of polysilicon having an n-type dopant, and wherein the diodes are formed by forming p-type regions in the first conductive lines. 
   
   
       8 . The mask ROM of  claim 1 , further comprising:
 a plurality of contacts, each disposed between a respective one of the diodes and a respective one of the final vias.   
   
   
       9 . The mask ROM of  claim 1 , further comprising:
 a passivation layer disposed on the second conductive lines.   
   
   
       10 . The mask ROM of  claim 1 , further comprising:
 a plurality of strapping lines, each coupled to a respective one of the first conductive lines.