Semiconductor device and method for manufacturing same

Abstract

When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

1 - 5 . (canceled) 
     
     
         6 . A method for manufacturing a semiconductor device comprising one substrate including a first device formation region and a second device formation region, in which the first device formation region has: a first semiconductor substrate portion of a first conductive type; a semiconductor layer formed above the first semiconductor substrate portion interposing an insulator layer; a first source region and a first drain region of a second conductive type which is a conductive type opposite to the first conductive type formed in the semiconductor layer; a first channel region formed between the first source region and the first drain region; a first gate insulating film formed on the first channel region; and a first gate electrode formed above the first channel region interposing the first gate insulating film formed therein, the second device formation region has: a second semiconductor substrate portion of the first conductive type; a second source region and a second drain region of the second conductive type formed in the second semiconductor substrate portion; a second channel region formed between the second source region and the second drain region; a second gate insulating film formed on the second channel region; and a second gate electrode formed above the second channel region interposing the second gate insulating film formed therein,
 wherein the first source region and the second source region, and the first drain region and the second drain region are formed in a same step, the first gate insulating film and the second gate insulating film are formed in a same step, and the first gate electrode and the second gate electrode are formed in a same step.   
     
     
         7 . The method for manufacturing the semiconductor device according to  claim 6 ,
 wherein the first gate electrode and the second gate electrode are formed of Ni, Co, Ti, W, Ta, Mo, Cr, Al, Pt, Pa, Ru, a silicide film thereof, or a nitride film thereof.   
     
     
         8 . A semiconductor device comprising an SOI-type MISFET formed on a surface of a semiconductor layer on a buried insulating film and a bulk-type MISFET formed on a surface of a semiconductor substrate,
 wherein a dummy pattern comprised by the semiconductor substrate, the buried insulating film formed thereon, and the semiconductor layer formed thereon is provided around a formation region of the bulk-type MISFET.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein a device is not formed on a surface of the semiconductor layer of the dummy pattern.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein a device isolation insulating film is provided between the dummy pattern and the bulk-type MISFET.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein a plurality of the dummy patterns having a same planar shape are arranged so as to surround the formation region of one of the bulk-type MISFET, and the device isolation insulating film is provided between each of the dummy patterns.   
     
     
         12 . A method for manufacturing a semiconductor device having an SOI-type MISFET and a bulk-type MISFET mounted in a mixed manner on a same substrate,
 the method comprising the steps of:   preparing an SOI substrate formed of a semiconductor substrate, a buried insulating film formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating film;   removing the semiconductor layer and the buried insulating film in a formation region for the bulk-type MISFET to expose a surface of the semiconductor substrate;   forming a first insulating film on the whole surface such that a film thickness thereof is thicker than a thickness obtained by adding film thicknesses of the semiconductor layer and the buried insulating film;   removing the first insulting film in a device isolation region;   removing the semiconductor layer, the buried insulating film, and the semiconductor substrate in a portion not having the first insulating film formed thereabove to form a trench in the device isolation region;   forming a second insulating film different from the first insulating film on the whole surface to fill in the groove; and   removing the second insulating film excluding the same in the device isolation region by chemical mechanical polishing to expose a surface of the first insulating film.   
     
     
         13 . The method for manufacturing the semiconductor device according to  claim 12  further comprising the steps of:
 removing the exposed first insulating film; and   forming the SOI-type MISFET and the bulk-type MISFET on the semiconductor layer surface in the formation region for the SOI-type MISFET and the semiconductor substrate surface in the formation region for the bulk-type MISFET, respectively.   
     
     
         14 . The method for manufacturing the semiconductor device according to  claim 12 ,
 wherein the first insulating film and the second insulating film have a different polishing rate for each chemical mechanical polishing thereof.   
     
     
         15 . The method for manufacturing the semiconductor device according to  claim 13 ,
 wherein the first insulating film and the second insulating film have a different polishing rate for each chemical mechanical polishing thereof.   
     
     
         16 . The method for manufacturing the semiconductor device according to  claim 12 ,
 wherein the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.   
     
     
         17 . The method for manufacturing the semiconductor device according to  claim 13 ,
 wherein the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.   
     
     
         18 . The method for manufacturing the semiconductor device according to  claim 16 ,
 wherein the silicon nitride film is used as a polishing stopper for chemical mechanical polishing.   
     
     
         19 . The method for manufacturing the semiconductor device according to  claim 17 ,
 wherein the silicon nitride film is used as a polishing stopper for chemical mechanical polishing.   
     
     
         20 . A method for manufacturing a semiconductor device including an SOI-type MISFET and a bulk-type MISFET,
 the method comprising the steps of:   removing a semiconductor layer and a buried insulating film of an SOI substrate in a formation region for the bulk-type MISFET to expose a surface of a semiconductor substrate;   forming a gate electrode material film above each of the semiconductor layer in a formation region for the SOI-type MISFET and the semiconductor substrate in the formation region for the bulk-type MISFET; and   patterning the gate electrode material film to form a first gate electrode of the SOI-type MISFET and a second gate electrode of the bulk-type MISFET,   wherein, in the step of forming the first gate electrode and the second gate electrode, the step is performed making a focus depth of photolithography adjusted to be focused on the side of the formation region for the SOI-type MISFET.   
     
     
         21 . The method for manufacturing the semiconductor device according to  claim 20 ,
 wherein a dimension of the second gate electrode is made larger than that of the first gate electrode.   
     
     
         22 . The method for manufacturing the semiconductor device according to  claim 21 ,
 wherein the gate electrode material film includes a polycrystalline silicon film.   
     
     
         23 . A method for manufacturing a semiconductor device comprising the steps of:
 preparing an SOI substrate formed of a semiconductor substrate, a buried insulating film formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating film;   removing the semiconductor layer and the buried insulating film partially to expose part of a surface of the semiconductor substrate;   forming a first insulating film on the exposed semiconductor substrate surface;   forming a gate insulating film on the surface of the semiconductor substrate;   forming a gate electrode material film on the whole surface including the gate insulating film and the first insulating film;   forming a second insulating film on the gate electrode material film;   patterning the gate electrode material film and the second insulating film to form a gate electrode formed astride the gate insulating film and the first insulating film,   forming source and drain regions in the semiconductor layer;   forming a hole penetrating the gate electrode and the first insulating film and exposing the surface of the semiconductor substrate; and   forming a silicon film on the source and drain regions and on the surface of the semiconductor substrate exposed through the hole by selective epitaxial growth.   
     
     
         24 . The method for manufacturing a semiconductor device according to  claim 23 ,
 wherein the selective epitaxial growth is performed until an upper surface of the silicon film formed inside the hole becomes higher than a lower surface of the gate electrode.   
     
     
         25 . The method for manufacturing a semiconductor device according to  claim 24  further comprising a step of forming a third insulating film covering a side surface of the gate electrode between the step of forming the gate electrode and the step of forming the hole. 
     
     
         26 . A method for manufacturing a semiconductor device having an SOI-type MISFET of a first conductive type and a bulk-type MISFET of the first conductive type mounted on a same substrate in a mixed manner,
 the method comprising the steps of:   preparing an SOI substrate formed of a semiconductor substrate, a buried insulating film formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating film;   removing the semiconductor layer and the buried insulating film in a formation region for the bulk-type MISFET to expose a surface of the semiconductor substrate;   respectively forming a first gate insulating film on the semiconductor layer in a formation region for the SOI-type MISFET and a second gate insulating film on the surface of the semiconductor substrate in the formation region for the bulk-type MISFET;   respectively forming a first gate electrode of the SOI-type MISFET on the first gate insulating film and a second gate electrode of the bulk-type MISFET on the second gate insulating film;   simultaneously forming shallow first source and drain diffusion layers of the first conductive type in the semiconductor layer in the formation region for the SOI-type MISFET and shallow second source and drain diffusion layers of the first conductive type in the semiconductor substrate in the formation region for the bulk-type MISFET respectively, by ion implantation using the first gate electrode and the second gate electrode as masks;   forming a first gate sidewall insulating film on side faces of the first gate electrode and a second gate sidewall insulating film on side surfaces of the second gate electrode respectively; and   respectively forming deep third source and drain diffusion layers of the first conductive type in the semiconductor substrate in the formation region for the SOI-type MISFET and deep fourth source and drain diffusion layers of the first conductive type in the semiconductor substrate in the formation region for the bulk-type MISFET by ion implantation using the first gate electrode, the first gate sidewall insulating film, the second gate electrode, and the second gate sidewall insulating film as masks.   
     
     
         27 . The method for manufacturing a semiconductor device according to  claim 26 ,
 wherein the third source and drain diffusion layers are formed so as to contact with a lower surface of the buried insulating film in the formation region for the SOI-type MISFET.   
     
     
         28 . The method for manufacturing a semiconductor device according to  claim 27 ,
 wherein the third source and drain diffusion layers have a function of reducing parasitic capacitance of the first source and drain diffusion layers.