Sram device

Abstract

An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.

1 . An SRAM device using a four-terminal double gate field effect transistor as a selection transistor,
 wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and   wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation.   
   
   
       2 . The SRAM device according to  claim 1 , wherein the gate which controls the threshold voltage of the selection transistor is connected to wires arranged in a column direction parallel with a bit line. 
   
   
       3 . The SRAM device according to  claim 1 , further comprising, on each column, a circuit which calculates the logical product of a write enable signal and a column selection signal which is output from a column decoder, and generates a bias voltage according to the result. 
   
   
       4 . The SRAM device according to  claim 1 ,
 wherein a signal potential of a word line is adjusted so as to reduce a current leakage which flows through a bit line in a cell belonging to a row without being selected.   
   
   
       5 . The SRAM device according to  claim 4 , further comprising, on each row, a circuit which determines the signal potential suitable to an operation of a corresponding row on the basis of a row selection signal of a row decoder, and outputs the signal potential to a word line.