Cpu power delivery system

Abstract

A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.

1 . A central processing unit (CPU) comprising:
 a CPU die, including;
 a first processing core; 
 a second processing core; and 
   a voltage regulator die bonded to the CPU die in a three dimensional packaging configuration, including:
 a first voltage regulator module (VRM) to supply a first voltage to the first processing core; and a second VRM to supply a second voltage to the second processing core. 
   
   
   
       2 . The CPU of  claim 1  wherein the first voltage is equal to the second voltage. 
   
   
       3 . The CPU of  claim 1  wherein the voltage regulator die further comprises:
 a third VRM to supply a third voltage to a cache at the CPU die; and   a fourth VRM to supply a fourth voltage to an input/output (I/O) circuitry at the CPU die.   
   
   
       4 . The CPU of  claim 3  further comprising I/O connections coupled between the voltage regulator die and the CPU die. 
   
   
       5 . The CPU of  claim 1  further comprising a package substrate bonded to the voltage regulator die. 
   
   
       6 . The CPU of  claim 5  wherein the voltage regulator die is pad matched to the CPU die and the package substrate. 
   
   
       7 . The CPU of  claim 1  wherein the voltage regulator die is flipped and bonded to the CPU die metal side to metal side. 
   
   
       8 . A method comprising bonding a voltage regulator die to a central processing unit (CPU) die in a three-dimensional packaging configuration. 
   
   
       9 . The method of  claim 8  further comprising bonding a package substrate to the voltage regulator die. 
   
   
       10 . The method of  claim 9  wherein the voltage regulator die is pad matched to the CPU die and the package substrate. 
   
   
       11 . The method of  claim 8  further comprising coupling I/O connections between the voltage regulator die and the CPU die. 
   
   
       12 . The method of  claim 8  further comprising:
 supplying a first voltage to a first processing core on the CPU die with a first voltage regulator module (VRM) on the voltage regulator die; and   supplying a second voltage to a second processing core on the CPU die with a second VRM on the voltage regulator die   
   
   
       13 . A system comprising:
 a central processing unit (CPU) having:   a CPU die, including;
 a first processing core; 
 a second processing core; and 
   a voltage regulator die bonded to the CPU die in a three dimensional packaging configuration, including:
 a first voltage regulator module (VRM) to supply a first voltage to the first processing core; 
 a second VRM to supply a second voltage to the second processing core; 
   a chipset coupled to the CPU; and   a main memory device coupled to the chipset.   
   
   
       14 . The system of  claim 13  wherein the voltage regulator die further comprises:
 a third VRM to supply a third voltage to a cache at the CPU die; and   a fourth VRM to supply a fourth voltage to an input/output (I/O) circuitry at the CPU die.   
   
   
       15 . The system of  claim 14  further comprising I/O connections coupled between the voltage regulator die and the CPU die. 
   
   
       16 . The system of  claim 13  wherein the CPU further comprises a package substrate bonded to the voltage regulator die. 
   
   
       17 . The system of claim  65  wherein the voltage regulator die is pad matched to the CPU die and the package substrate. 
   
   
       18 . The system of  claim 13  wherein the voltage regulator die is flipped and bonded to the CPU die metal side to metal side.