Analog circuit cell array and analog integrated circuit

Abstract

An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

1 . An analog circuit cell array including a plurality of transistor cell arranged in an array, each of the transistor cells comprising:
 a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and   a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein   the first gate electrode and the second gate electrode are connected together for use, and   the first source region and the second source region are connected together for use.   
     
     
         2 . The analog circuit cell array according to  claim 1 , wherein the each transistor cell includes an interconnecting electrode for interconnecting the first gate electrode and the second gate electrode. 
     
     
         3 . The analog circuit cell array according to  claim 1 , wherein the first gate electrode and the second gate electrode of the each transistor cell extend outwardly of the first channel region and the second channel region, respectively, and are provided with interconnect contacts on outwardly extending portions. 
     
     
         4 . The analog circuit cell array according to  claim 1 , comprising a diffusion region, formed in an boundary area of the each transistor cell, for feeding a well in the each transistor cell. 
     
     
         5 . The analog circuit cell array according to  claim 1 , wherein no metal interconnect lines are placed above the first channel region and the second channel region of any transistor cell configured for use. 
     
     
         6 . The analog circuit cell array according to  claim 1 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells. 
     
     
         7 . The analog circuit cell array according to  claim 2 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells. 
     
     
         8 . The analog circuit cell array according to  claim 3 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells. 
     
     
         9 . The analog circuit cell array according to  claim 4 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells. 
     
     
         10 . The analog circuit cell array according to  claim 5 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells. 
     
     
         11 . The analog circuit cell array according to  claim 6 , wherein transistor cells of identical type are arranged in continuous fashion in four rows and four or more columns. 
     
     
         12 . An analog integrated circuit comprising: an analog circuit cell array including a plurality of transistor cell arranged in an array, each of the transistor cells comprising:
 a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and   a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein   the first gate electrode and the second gate electrode are connected together for use, and   the first source region and the second source region are connected together for use.   
     
     
         13 . The analog integrated circuit according to  claim 12 ,
 wherein the plurality of transistor cells include PMOS transistor cells and NMOS transistor cells, transistor cells of identical type are arranged in continuous fashion in four rows and four or more columns; and   wherein the analog integrated circuit comprises a transistor pair arranged in a common centroid configuration by using 2×2 transistor cells located in a center area of a section in which the transistor cells of identical type are arranged in continuous fashion in four rows and four or more columns.   
     
     
         14 . The analog integrated circuit according to  claim 13 , comprising a transistor cell connected to the first gate electrode and the second gate electrode of two transistor cells contained in the pair arranged in a common centroid configuration.