Chip package structure

Abstract

A chip package includes a die, a pad-mounting surface on the die, a plurality of bonding pad arranged at the pad-mounting surface, at least one dielectric layer cover over the pad-mounting surface, and at least one conductive wire set in the dielectric layer. The formation of the conductive wire consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

1 . A chip package that is assembled on a substrate and is electrically connected with a plurality of solder points arranged at the substrate comprising: a die, at least one dielectric layer and at least one conductive wire; wherein
 the die having a pad-mounting surface disposed with a plurality of bonding pads;   the dielectric layer covered over the pad-mounting surface of the die;   the conductive wire arranged in the dielectric layer and one end of each conductive wire is electrically connected with one bonding pad of the die while the other end of the conductive wire extends outward and exposes outside surface of the dielectric layer to form a solder point that is electrically connected with a preset solder point on a substrate for connecting and assembling the die on the substrate; the conductive wire is formed by:   coating a first dielectric layer on the pad-mounting surface of the die;   forming a slot on the first dielectric layer by exposure and development of photoresist materials while the slot corresponding to each bonding pad on the pad-mounting surface so that each bonding pad is exposed through each slot;   coating a second dielectric layer on the first dielectric layer and each bonding pad;   forming a wiring slot on the second dielectric layer by exposure and development of photoresist materials while the wiring slot connects with each bonding pad and the slot of the bonding pad; each wiring slot is mounted concavely in the second dielectric layer;   filling electrically conductive metal into each wiring slot to form a respective conductive wire;   coating a third dielectric layer on the second dielectric layer and each conductive wire;   forming a slot on the third dielectric layer by exposure and development of photoresist materials and the slot connected with one end of each conductive wire; and   filling electrically conductive metal into each slot to form a respective solder point that is exposed outside the third dielectric layer to be electrically connected with each bonding pad of the die.   
   
   
       2 . The device as claimed in  claim 1 , wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are coated by spin coating. 
   
   
       3 . The device as claimed in  claim 1 , wherein before the step of coating a second dielectric layer, each bonding pad exposed through each slot is coated with an electrically conductive metal layer that is used as a protective layer for each bonding pad. 
   
   
       4 . The device as claimed in  claim 1 , wherein the electrically conductive metal is filled into each wiring slot and into each slot by metal paste printing, sputter, chemical vapor deposition (CVD), sputtering and electroplating, or CVD and electroplating. 
   
   
       5 . The device as claimed in  claim 1 , wherein the solder point exposed outside the dielectric layer is a hemisphere, projecting out of the dielectric layer. 
   
   
       6 . A chip package that is assembled on a substrate and is electrically connected with a plurality of solder points arranged at the substrate comprising: a die, at least one dielectric layer and at least one conductive wire; wherein:
 the die having a pad-mounting surface disposed with a plurality of bonding pads;   the dielectric layer covered over the pad-mounting surface of the die;   the conductive wire arranged in the dielectric layer and one end of each conductive wire is electrically connected with one bonding pad of the die while the other end of the conductive wire extends outward and exposes outside surface of the dielectric layer to form a solder point that is electrically connected with a preset solder point on a substrate for connecting and assembling the die on the substrate; the conductive wire is formed by:   coating a first dielectric layer on the pad-mounting surface of the die;   forming a slot on the first dielectric layer by exposure and development of photoresist materials while the slot corresponding to each bonding pad on the pad-mounting surface so that each bonding pad is exposed through the slot;   coating a second dielectric layer on the first dielectric layer and each bonding pad;   forming a wiring slot or a slot on the second dielectric layer by exposure and development of photoresist materials while the wiring slot or the slot connects with each bonding pad and the slot of the bonding pad; part of the bonding pad and the slot thereof forms a wiring slot and the rest part of the bonding pad and the slot thereof forms a slot while each wiring slot and each slot are mounted concavely in the second dielectric layer;   filling electrically conductive metal into each wiring slot and each slot to form a lower-layer conductive wire respectively;   coating a third dielectric layer on the second dielectric layer and each lower-layer conductive wire;   forming a slot on the third dielectric layer by exposure and development of photoresist materials and the slot connected with one end of each lower-layer conductive wire;   coating a fourth dielectric layer on the third dielectric layer and each slot;   forming a wiring slot or a slot on the fourth dielectric layer by exposure and development of photoresist materials and the wiring slot or the slot connected with one end of each lower-layer conductive wire; part of the lower-layer conductive wire forms a slot when the part of the lower-layer conductive wire is a wiring slot in the second dielectric layer while the rest part of the lower-layer conductive wire forms a slot wiring when the part of the lower-layer conductive wire is a slot in the second dielectric layer; wherein each wiring slot and each slot are mounted concavely in the fourth dielectric layer;   filling electrically conductive metal into each wiring slot and each slot to form an upper-layer conductive wire respectively;   coating a fifth dielectric layer on the fourth dielectric layer and each upper-layer conductive wire;   forming a slot on the fifth dielectric layer by exposure and development of photoresist materials and the slot connected with one end of each upper-layer conductive wire; and   filling electrically conductive metal into each slot on the fifth dielectric layer to form a respective solder point that is exposed outside the fifth dielectric layer to be electrically connected with each bonding pad of the die.   
   
   
       7 . The device as claimed in  claim 6 , wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are coated by spin coating but not limiting. 
   
   
       8 . The device as claimed in  claim 6 , wherein before the step of coating a second dielectric layer, each bonding pad exposed through each slot is coated with an electrically conductive metal layer that is used as a protective layer for each bonding pad. 
   
   
       9 . The device as claimed in  claim 6 , wherein before the step of coating a fifth dielectric layer, each bonding pad exposed through each slot is coated with an electrically conductive metal layer that is used as a protective layer for each bonding pad. 
   
   
       10 . The device as claimed in  claim 6 , wherein the electrically conductive metal is filled into each wiring slot and into each slot by silver paste printing, sputter, chemical vapor deposition (CVD), sputtering and electroplating, or CVD and electroplating. 
   
   
       11 . The device as claimed in  claim 6 , wherein the solder point exposed outside the dielectric layer is a hemisphere, projecting out of the dielectric layer.