US2010155114A1PendingUtilityA1

Package for semiconductor devices

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Assignee: SHINKO ELECTRONICSPriority: May 30, 2003Filed: Feb 24, 2010Published: Jun 24, 2010
Est. expiryMay 30, 2023(expired)· nominal 20-yr term from priority
H05K 1/0271H05K 2201/0133B41J 15/16H05K 2201/0278B41J 11/006H05K 3/4688H05K 2201/029H05K 2201/0141H05K 2201/068B41J 11/66B41J 11/009H05K 2201/09036H05K 2201/10674H05K 1/0366B41J 11/04H10W 72/07251H10W 72/20H10W 70/682H10W 70/655H10W 70/695H10W 70/685
48
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Claims

Abstract

To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

Claims

exact text as granted — not AI-modified
1 . A package for a semiconductor device, comprising a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other, at least two insulating resin layers laminated on an upper surface of said laminate and including a first layer serving as an uppermost layer and a second layer forming a next layer under the uppermost layer, and a portion defined on an upper surface of said first layer and for mounting a semiconductor element, wherein said first layer is constituted by an insulating resin having a coefficient of linear thermal expansion smaller than a coefficient of linear thermal expansion of the semiconductor element that is to be mounted, and said second layer is constituted by a material having a low Young's modulus and a high percentage of elongation. 
   
   
       2 . A package for a semiconductor device according to  claim 1 , wherein a reinforcing member is secured to said first layer so as to surround the portion for mounting the semiconductor element. 
   
   
       3 . A package for a semiconductor device according to  claim 1 , wherein said first layer has a slit formed along a periphery of the portion for mounting the semiconductor element to absorb a difference in stress between the portion for mounting the semiconductor element and a surrounding region. 
   
   
       4 . A package for a semiconductor device, comprising a laminate including a plurality of alternating conducting layers and insulating layers that are alternately laminated upon one another, at least one insulating layer including a first layer serving as an uppermost layer, and a portion defined on an upper surface of said first layer and for mounting a semiconductor element, wherein said first layer is constituted by a material having a low Young's modulus and a high percentage of elongation. 
   
   
       5 . A package for a semiconductor device according to  claim 4 , wherein a reinforcing member is secured to said first layer so as to surround the portion for mounting the semiconductor element. 
   
   
       6 . A package for a semiconductor device according to  claim 4 , wherein said first layer has a slit formed along a periphery of the portion for mounting the semiconductor element to absorb a difference in stress between the portion for mounting the semiconductor element and a surrounding region. 
   
   
       7 . A package for a semiconductor device, comprising a laminate including a plurality of alternating conducting layers and insulating resin layers alternately laminated upon one another, at least one insulating resin layer laminated on an upper surface of said laminate and including at least a first layer serving as an uppermost layer, and a portion defined on the upper surface of said first layer and for mounting a semiconductor element, wherein at least a region of said portion for mounting the semiconductor element of said first layer has a plurality of grooves or slits formed therein for reducing stress.

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