Package for semiconductor devices

Abstract

To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

1 . An interposer interposed between a semiconductor element and a package having a portion for mounting said semiconductor element to electrically connect a plurality of electrode terminals of the semiconductor element to a plurality of pad portions of the package, said interposer comprising a plate-like interposer body made of an elastic material having rubbery elasticity, a plurality of first terminals protruding from one surface of said interposer body joined to the plurality of electrode terminals of said semiconductor element, and a plurality of second terminals protruding from another surface of said interposer body joined to said plurality of pad portions of said package. 
   
   
       2 . An interposer according to claim  7 , wherein said interposer body contains an insulating mesh therein. 
   
   
       3 . A package for a semiconductor device, comprising a laminate including a plurality of alternating conducting layers and insulating resin layers alternately laminated upon one another, at least one insulating resin layer laminated on an upper surface of said laminate and including at least a first layer serving as an uppermost surface layer, and a portion defined on the uppermost surface of said first layer and for mounting a semiconductor element, wherein said first layer is a stress buffer layer having rubbery elasticity. 
   
   
       4 . A package for a semiconductor device according to claim  10 , wherein said first layer which comprises the stress buffer layer includes an insulating mesh therein.