Semiconductor package, manufacturing method thereof and ic chip

Abstract

A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire. The bump land and the wire land may be spaced apart from each other on an active surface of the IC chip.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor package comprising:
 a first semiconductor chip comprising a bump land, an I/O terminal and a chip bump bonded to the bump land;   a first chip substrate on which the first semiconductor chip is attached, the first chip substrate including a first bonding pad;   a wire connecting the first bonding pad and the I/O terminal   a package substrate including a second bonding pad disposed on an upper surface of the package substrate, the chip bump being bonded to the second bonding pad; and   a molding material extending between and contacting the upper surface of the package substrate and an opposing surface of the first chip substrate, extending between and contacting the upper surface of the package substrate and an opposing surface of the first semiconductor chip, the molding material contacting the upper surface of the package substrate adjacent the chip bump, contacting the opposing surface of the first semiconductor chip adjacent the chip bump, and surrounding the chip bump to fully encapsulate the chip bump so that no part of the chip bump remains exposed.   
     
     
         22 . The semiconductor package of  claim 21 ,
 wherein the bump land of the first semiconductor chip, the chip bump of the first semiconductor chip and the I/O terminal of the first semiconductor chip are arranged on the opposing surface of the first semiconductor chip.   
     
     
         23 . The semiconductor package of  claim 22 , further comprises:
 a passivation layer provided at the opposing surface of the first semiconductor chip and a portion of the I/O terminal; and   a conductive layer disposed on the passivation layer and connected to the bump land of the first semiconductor chip.   
     
     
         24 . The semiconductor package of  claim 23 , wherein the conductive layer extends through the passivation layer to contact the I/O terminal of the first semiconductor chip. 
     
     
         25 . The semiconductor package of  claim 24 , wherein the bump land of the first semiconductor chip comprises a portion of the conductive layer. 
     
     
         26 . The semiconductor package of  claim 25 , wherein the bump land of the first semiconductor chip is spaced apart from the I/O terminal of the first semiconductor chip. 
     
     
         27 . The semiconductor package of  claim 26 , further comprising an external connection terminal pad disposed at a lower surface of the package substrate. 
     
     
         28 . The semiconductor package of  claim 23 , wherein the wire is connected to a wire land comprising a portion of the conductive layer. 
     
     
         29 . The semiconductor package of  claim 28 , wherein the wire land and the bump land of the first semiconductor chip are disposed on the passivation layer. 
     
     
         30 . A semiconductor package comprising:
 a first semiconductor chip comprising a bump land, an I/O terminal and a chip bump bonded to the bump land;   a first chip substrate on which the first semiconductor chip is attached, the first chip substrate including a first bonding pad;   a first wire connecting the first bonding pad and the I/O terminal   a package substrate including a second bonding pad disposed on an upper surface of the package substrate, the chip bump being bonded to the second bonding pad;   a molding material extending between and contacting the upper surface of the package substrate and an opposing surface of the first chip substrate, extending between and contacting the upper surface of the package substrate and an opposing surface of the first semiconductor chip, the molding material contacting the upper surface of the package substrate adjacent the chip bump of the first semiconductor chip, contacting the opposing surface of the first semiconductor chip adjacent the chip bump of the first semiconductor chip, and surrounding the chip bump of the first semiconductor chip to fully encapsulate the chip bump of the first semiconductor chip so that no part of the chip bump of the first semiconductor chip remains exposed;   a second semiconductor chip comprising a bump land and a chip bump bonded to the bump land of the second semiconductor chip; and   a second chip substrate on which the second semiconductor chip is attached,   wherein the first chip substrate further comprises a third bonding pad to which the chip bump of the second semiconductor chip is bonded,   wherein the first chip substrate includes an electrical connection of the third bonding pad to the first chip bonding pad, and   wherein the molding material extends between and contacts the upper surface of the package substrate and an opposing surface of the second chip substrate.   
     
     
         31 . The semiconductor package of  claim 30 , wherein the molding material encapsulates the first chip substrate. 
     
     
         32 . The semiconductor package of  claim 30 ,
 wherein the bump land of the first semiconductor chip, the chip bump of the first semiconductor chip and the I/O terminal of the first semiconductor chip are arranged at the opposing surface of the first semiconductor chip.   
     
     
         33 . The semiconductor package of  claim 32 , wherein the bump land of the second semiconductor chip, the chip bump of the second semiconductor chip and the I/O terminal of the second semiconductor chip are arranged at a surface of the second semiconductor chip which faces the package substrate. 
     
     
         34 . The semiconductor package of  claim 33 , further comprises:
 a first passivation layer provided at the opposing surface of the first semiconductor chip and on a portion of the I/O terminal of the first semiconductor chip;   a first rerouting line disposed on the first passivation layer and connected to the first bump land;   a second passivation layer provided at the surface of the second semiconductor chip which faces the package substrate and on a portion of the second I/O terminal; and   a second rerouting line disposed on the second passivation layer and connected to the second bump land.   
     
     
         35 . The semiconductor package of  claim 34 ,
 wherein the first wire is connected to a first wire land comprising a portion of the first rerouting line,   wherein the semiconductor package further comprises a second wire connected to a fourth chip bonding pad at a surface of the second chip substrate and a second wire land comprising a portion of the second rerouting line,   wherein the first rerouting line extends through the first passivation layer,   wherein the second rerouting line extends through the second passivation layer.   
     
     
         36 . The semiconductor package of  claim 34 , wherein the bump land of the first semiconductor chip comprises a portion of the first rerouting line and the bump land of the second semiconductor chip comprises a portion of the second rerouting line. 
     
     
         37 . The semiconductor package of  claim 36 , wherein the bump land of the first semiconductor chip is spaced apart from the I/O terminal of the first semiconductor chip and the bump land of the second semiconductor chip is spaced apart from the I/O terminal of the second semiconductor chip. 
     
     
         38 . The semiconductor package of  claim 33 , wherein the first semiconductor chip and the second semiconductor chip are different types of chips. 
     
     
         39 . The semiconductor package of  claim 38 , a width of the second semiconductor chip is larger than a width of the first semiconductor chip. 
     
     
         40 . The semiconductor package of  claim 33 , wherein the first semiconductor chip and the second semiconductor chip are a same type of chip. 
     
     
         41 . The semiconductor package of  claim 33 , further comprising a solder ball bonded to an external connection terminal pad of the package substrate. 
     
     
         42 . A semiconductor package comprising:
 a first semiconductor chip comprising a bump land, an I/O terminal and a chip bump bonded to the bump land;   a first chip substrate including an upper surface and a lower surface, the first semiconductor chip being attached at the lower surface of the first chip substrate, the first chip substrate comprising a first bonding pad at the lower surface of the first chip substrate;   a first wire connecting the first bonding pad and the I/O terminal   a package substrate including a second bonding pad disposed on an upper surface of the package substrate, the chip bump of the first semiconductor chip being bonded to the second bonding pad;   a first molding material extending between and contacting the upper surface of the package substrate and an opposing surface of the first chip substrate, extending between and contacting the upper surface of the package substrate and an opposing surface of the first semiconductor chip, the first molding material contacting the upper surface of the package substrate adjacent the chip bump of the first semiconductor chip, contacting the opposing surface of the first semiconductor chip adjacent the chip bump of the first semiconductor chip, and surrounding the chip bump of the first semiconductor chip to fully encapsulate the chip bump of the first semiconductor chip so that no part of the chip bump of the first semiconductor chip remains exposed;   a second semiconductor chip comprising a bump land and a chip bump bonded to the bump land of the second semiconductor chip;   a second chip substrate on which the second semiconductor chip is attached and comprising a terminal at an upper surface of the second chip substrate;   a third semiconductor chip comprising a bump land and a chip bump bonded to the bump land of the third semiconductor chip and to the terminal of the second semiconductor chip substrate;   a third chip substrate comprising a lower surface on which the third semiconductor chip is attached; and   a second molding resin extending between and contacting the lower surface of the third circuit substrate and the upper surface of the second circuit substrate.