Reducing warpage for fan-out wafer level packaging

Abstract

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

1 . A method of manufacturing fan-out wafer level packaging, the method comprising:
 positioning an integrated circuit on a first surface;   forming a layer of encapsulant on the first surface substantially surrounding the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit;   forming a redistribution layer configured to electrically couple a bond pad of the integrated circuit to a redistributed bond pad; and   forming a bump at the redistributed bond pad.   
     
     
         2 . The method of  claim 1 , wherein positioning the integrated circuit on the first surface includes positioning the integrated circuit on an adhesive surface of a piece of tape. 
     
     
         3 . The method of  claim 2 , wherein the height of the layer of encapsulant is equal to the height of the integrated circuit. 
     
     
         4 . The method of  claim 3 , further comprising curing the encapsulant, and removing the piece of tape. 
     
     
         5 . The method of  claim 4 , wherein, upon removing the piece of tape, a top surface and a bottom surface of the integrated circuit are both exposed, and the layer of encapsulant substantially covers four side surfaces of the integrated circuit. 
     
     
         6 . The method of  claim 2 , wherein the integrated circuit is positioned on the adhesive surface with the bond pad of the integrated circuit facing the adhesive surface. 
     
     
         7 . The method of  claim 1 , wherein the height of the layer of encapsulant is less than 10% greater than the height of the integrated circuit. 
     
     
         8 . The method of  claim 1 , further comprising forming a first dielectric layer extending at least partially over a top surface of the integrated circuit, the first dielectric layer including a bond pad via through which at least a portion of the bond pad is exposed. 
     
     
         9 . The method of  claim 9 , wherein forming the redistribution layer includes forming the redistribution layer over at least a portion of the first dielectric layer, and filling at least partially the bond pad via with a portion of the redistribution layer. 
     
     
         10 . The method of  claim 9 , wherein forming the redistribution layer includes:
 sputtering a seed layer over the first dielectric layer and within the bond pad via;   forming a patterned layer over the seed layer using photolithography;   plating at least a portion of the seed layer exposed through the patterned layer to form the redistribution layer;   removing the patterned layer; and   removing at least a remaining portion of the seed layer that is not plated.   
     
     
         11 . The method of  claim 11 , wherein the redistribution layer includes the redistributed bond pad, and wherein forming the bump includes forming the bump in direct contact with the redistribution layer. 
     
     
         12 . The method of  claim 9 , further comprising forming a second dielectric layer extending at least partially over the redistribution layer, the second dielectric layer including a redistribution via through which at least a portion of the redistribution layer is exposed. 
     
     
         13 . The method of  claim 8 , further comprising, after forming the second dielectric layer, forming the redistributed bond pad at least partially within the redistribution via. 
     
     
         14 . A method of manufacturing fan-out wafer level packaging, the method comprising:
 positioning an active surface of an integrated circuit on a first surface;   placing an inactive surface of the integrated circuit in an encapsulant in a molding chamber; and   compressing the first surface towards the encapsulant in the molding chamber to cover all sides of the integrated circuit with encapsulant and to prevent the encapsulant from covering the inactive surface and the active surface of the integrated circuit.   
     
     
         15 . The method of  claim 14 , further comprising compressing the first surface until the inactive surface of the integrated circuit is adjacent a bottom interior surface of the molding chamber. 
     
     
         16 . The method of  claim 15 , further comprising protecting the integrated circuit by forming a protective layer adjacent the bottom interior surface of the molding chamber. 
     
     
         17 . The method of  claim 14 , further comprising removing the integrated circuit from the molding chamber and removing the first surface from the integrated circuit. 
     
     
         18 . The method of  claim 17  wherein a height of the encapsulant is substantially equal to a height of the integrated circuit. 
     
     
         19 . The method of  claim 17 , further comprising forming a redistribution layer configured to electrically couple a bond pad of the integrated circuit to a redistributed bond pad. 
     
     
         20 . The method of  claim 19 , further comprising forming a bump on the redistributed bond pad. 
     
     
         21 . A method of forming an encapsulation layer for fan-out wafer level packaging, comprising:
 positioning a first surface of an integrated circuit on a carrier; and   compressing the integrated circuit into a molding chamber having an encapsulant therein, the molding chamber sized and shaped to allow a second surface of the integrated circuit to contact a bottom surface of the molding chamber.   
     
     
         22 . The method of  claim 21  wherein the integrated circuit is compressed into the molding chamber by applying a force to a surface of the carrier not in contact with the integrated circuit. 
     
     
         23 . The method of  claim 21  wherein the bottom surface of the molding chamber is covered with a protective layer to prevent damage to the integrated circuit. 
     
     
         24 . The method of  claim 21  wherein the carrier includes an adhesive layer and a support layer, the integrated circuit separated from the support layer by the adhesive layer.