Pmos pixel structure with low cross talk for active pixel image sensors

Abstract

An image sensor with an image area having a plurality of pixels each having a photodetector of a first conductivity type, the image sensor includes a substrate of the first conductivity type; a first layer of the second conductivity type between the substrate and the photodetectors, spanning the image area and biased at predetermined potential with respect to the substrate for driving excess carriers into the substrate to reduce cross talk; one or more adjacent active electronic components disposed in the first layer within each pixel; and electronic circuitry disposed in the substrate outside of the image area.

1 . An image sensor including an image area having a plurality of pixels with at least one pixel having a photodetector of a p conductivity type which use holes as charge carriers, the image sensor comprising:
 a substrate of the p conductivity type;   a first layer of n conductivity type between the substrate and the at least one p-type photodetector, wherein the first layer spans the entire image area having the plurality of pixels; and   a contact electrically connected to the first layer for biasing the first later at a predetermined potential with respect to the substrate for driving excess carriers into the substrate to reduce cross talk.   
     
     
         2 . The image sensor as in  claim 1 , further comprising:
 one or more adjacent active P-channel Metal Oxide Semiconductor (PMOS) electronic components disposed in the first layer with the at least one pixel; and   CMOS electronic support circuitry disposed in the substrate outside of the image area and electrically connected to the image area.   
     
     
         3 . The image sensor as in  claim 1 , further comprising an isolation region disposed adjacent to a portion of at least one photodetector. 
     
     
         4 . The image sensor as in  claim 3 , further comprising an isolation implant of n conductivity type surrounding at least a portion of at least one photodetector. 
     
     
         5 . The image sensor as in  claim 3 , wherein the isolation implant of n conductivity type comprises an arsenic implant region. 
     
     
         6 . The image sensor as in  claim 1 , further comprising a pinning layer of the n conductivity type. 
     
     
         7 . The image sensor as in  claim 6 , wherein the pinning layer of the n conductivity type comprises an arsenic implant region. 
     
     
         8 . The image sensor as in  claim 1 , wherein the photodetector of the p conductivity type comprises a boron implant region. 
     
     
         9 . The image sensor as in  claim 1 , further comprising a p-epitaxial layer disposed between the substrate and the first layer. 
     
     
         10 . The image sensor as in  claim 3 , further comprising a pinning layer of the n conductivity type connected to the isolation region. 
     
     
         11 . The image sensor as in  claim 2 , wherein the predetermined potential is set to a supply voltage connected to at least one PMOS electronic component. 
     
     
         12 . An image capture device, comprising:
 an image sensor including an image area having a plurality of pixels with at least one pixel having a photodetector of a p conductivity type which use holes as charge carriers, the image sensor comprising:   a substrate of the p conductivity type;   a first layer of n conductivity type between the substrate and the at least one p-type photodetector, wherein the first layer spans the entire image area having the plurality of pixels; and   a contact electrically connected to the first layer for biasing the first later at a predetermined potential with respect to the substrate for driving excess carriers into the substrate to reduce cross talk.   
     
     
         13 . A method for producing an image sensor including an imaging area having a plurality of pixels and a CMOS device area disposed outside of the imaging area, the method comprising:
 prior to producing any structures in the CMOS device area, forming a first layer of n conductivity type over a substrate of p conductivity type, wherein the first layer spans the entire image area; and   forming the plurality of pixels and at least one structure in the CMOS device area.