Field plate trench mosfet transistor with graded dielectric liner thickness

Abstract

An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.

1 . An electronic device, comprising:
 a plurality of trenches located within a semiconducting layer;   a vertical drift region between and adjacent said trenches;   an electrode located within each trench, said electrode having a gate electrode section and a field plate section; and   a graded field plate dielectric located between said field plate section and said vertical drift section.   
     
     
         2 . The electronic device recited in  claim 1 , wherein said second thickness is at least about 20% greater than said first thickness. 
     
     
         3 . The electronic device recited in  claim 1 , wherein a thickness of said field plate dielectric increases about linearly with increasing depth of said trench. 
     
     
         4 . The electronic device recited in  claim 1 , wherein a thickness of said field plate dielectric increases in a stepwise fashion from said top of said field plate to said bottom of said field plate. 
     
     
         5 . The electronic device recited in  claim 1 , wherein said field plate includes two or more regions, each region having a substantially uniform thickness. 
     
     
         6 . The electronic device recited in  claim 1 , wherein an electric field in said drift region in varies by less than about 30% of a maximum value in a direction parallel to said field plate. 
     
     
         7 . The electronic device recited in  claim 1 , further comprising an insulating layer located between a deep section of said field plate and a shallow section of said field plate. 
     
     
         8 . The electronic device recited in  claim 1 , wherein said field plate comprises polycrystalline silicon. 
     
     
         9 . A method of forming a vertical MOSFET, comprising:
 providing a semiconductor layer over a substrate, said semiconductor layer having a trench formed therein;   forming a gate dielectric on a top portion of a sidewall of said trench;   forming a field plate dielectric on a bottom portion of said sidewall, said field plate dielectric having a first portion with a first thickness at a first depth of said trench, and a second portion with a greater second thickness at a greater second depth of said trench, and   filling said trench with a field plate material.   
     
     
         10 . The method recited in  claim 9 , wherein forming said field plate dielectric comprises removing a portion of a dielectric layer formed over said sidewall. 
     
     
         11 . The method recited in  claim 10 , wherein forming said field plate dielectric further comprises removing a portion of a filler material thereby exposing said removed portion of said dielectric layer. 
     
     
         12 . The method recited in  claim 9 , wherein forming said field plate dielectric includes forming a mask layer over a portion of said sidewall that blocks formation of a dielectric layer on said sidewall. 
     
     
         13 . The method recited in  claim 9 , wherein forming said field plate dielectric comprises:
 forming a dielectric layer on said sidewall;   filling said trench with a sacrificial filler material;   removing a first portion of said sacrificial filler material, thereby exposing an upper portion of said dielectric layer; and   at least partially removing said exposed upper portion of said dielectric layer.   
     
     
         14 . The method recited in  claim 13 , further comprising:
 removing a second portion of said sacrificial filler material, thereby exposing a lower portion of said dielectric layer and leaving a remaining portion of said sacrificial filler material;   partially removing said exposed lower portion of said dielectric layer, leaving a remaining portion of said dielectric layer on said sidewalls; and   removing said remaining portion of said sacrificial filler material.   
     
     
         15 . The method recited in  claim 12 , further comprising deepening said trench after forming said mask layer. 
     
     
         16 . The method recited in  claim 11 , further comprising removing said mask layer after at least partially forming said second portion. 
     
     
         17 . The method recited in  claim 10 , further comprising removing a portion of said field plate dielectric after forming said portions with different thicknesses, thereby increasing a linearity of a change of thickness of said field plate dielectric with increasing depth of said trench. 
     
     
         18 . The method recited in  claim 9 , further comprising forming a gate oxide on said sidewall after forming said portions of said field plate dielectric. 
     
     
         19 . The method recited in  claim 13 , further comprising forming an insulating layer on an exposed surface of a remaining portion of said filler material; and
 filling said trench with a field plate material.   
     
     
         20 . The method recited in  claim 19 , further comprising forming a conductive path between said remaining portion and said field plate material. 
     
     
         21 . The method recited in  claim 9 , further comprising forming a first mask layer over sidewalls of said trench 
     
     
         22 . The method of  claim 21 , further comprising a first deepening of said trench after forming said first mask layer. 
     
     
         23 . The method of  claim 22 , further comprising forming a second mask layer over sidewalls of trench exposed by first deepening. 
     
     
         24 . The method of  claim 23 , further comprising a second deepening of said trench after forming said second mask layer. 
     
     
         25 . The method of  claim 24 , further comprising:
 forming a first oxide layer over a surface of said semiconductor layer exposed by said second deepening;   removing said second mask layer;   forming a second oxide liner over a surface of said semiconductor layer exposed by said first deepening; and   removing said first mask layer   
     
     
         26 . A vertical MOSFET comprising:
 an epitaxial layer located over a substrate, including:
 a body region adjacent an upper surface of said epitaxial layer and doped to have a first conductivity type; 
 a drain region located between said body region and said substrate and being doped to have a second conductivity type; 
 a buried region located between said drain region and said substrate and being doped to have said second conductivity type; and 
 a source region located within said body region and being doped to have said second conductivity type; 
   two trenches formed in said epitaxial layer;   polysilicon field plates, one field plate located within each of said trenches;   a drift region located within said drain region and between said field plates;   oxide liners located between each of said field plates and said drift region, a lower portion of each of said oxide liners having a thickness greater than a thickness of an upper portion of said oxide liners.   
     
     
         27 . The vertical MOSFET recited in  claim 26 , wherein said thickness of said lower portion is at least about 20% greater than said thickness of said upper portion. 
     
     
         28 . The vertical MOSFET recited in  claim 26 , wherein said thickness of said lower portion is substantially uniform over a vertical extent of said lower portion, and said thickness of said upper portion is substantially uniform over a vertical extent of said upper portion.