Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method

Abstract

A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.

1 - 8 . (canceled) 
     
     
         9 . A semiconductor device pattern data processing method comprising:
 acquiring a size of an overlapping area of each of a plurality of cells included in a cell library to be used to design a semiconductor device, the overlapping area being a region which is arranged inside the cell and in which placement of a functional pattern to impart a function to the cell is inhibited;   creating first design data by placing the plurality of cells;   calculating a first characteristic of the semiconductor device on the basis of the first design data;   extracting a correction target region in which, of patterns formed by combining the overlapping areas upon placing the plurality of cells, a pattern has a size not more than a threshold value;   generating second design data by correcting the correction target region contained in the first design data;   calculating a second characteristic of the semiconductor device on the basis of the second design data;   checking whether a characteristic difference between the first characteristic and the second characteristic falls within a tolerance; and   creating pattern data of the semiconductor device on the basis of the second design data when the characteristic difference falls within the tolerance.   
     
     
         10 . The method according to  claim 9 , wherein the overlapping area is provided not to violate a design rule regardless of the pattern of the cell to be placed adjacent. 
     
     
         11 . The method according to  claim 9 , wherein correcting the correction target region includes erasing the correction target region from the first design data. 
     
     
         12 . The method according to  claim 9 , wherein correcting the correction target region includes correcting the size of the correction target region, which is not more than the threshold value, to a size more than the threshold value. 
     
     
         13 . The method according to  claim 9 , wherein when the characteristic difference falls outside the tolerance, creating the pattern data on the basis of the first design data. 
     
     
         14 . The method according to  claim 9 , wherein the threshold value includes a minimum size of an implantation target region in an ion implantation process. 
     
     
         15 . The method according to  claim 9 , wherein letting T be the threshold value, 0.5≧T/(λ/NA) is satisfied where λ is a wavelength of light in exposure, and NA is a numerical aperture of a projection optical system of an exposure apparatus used in exposure. 
     
     
         16 . The method according to  claim 9 , wherein each of the first characteristic and the second characteristic includes at least one of a transistor characteristic, a circuit characteristic, an electrical characteristic, a timing characteristic, a wiring capacitance characteristic, and a wiring resistance characteristic. 
     
     
         17 . The method according to  claim 9 , further comprising:
 verifying manufacturability in an exposure process of the correction target region having the size not more than the threshold value when the characteristic difference falls outside the tolerance;   creating pattern data of the semiconductor device on the basis of the first design data when the manufacturability is more than a predetermined value;   generating third design data by correcting the correction target region contained in the first design data when the manufacturability is not more than the predetermined value;   executing optical proximity correction for the third design data; and   creating pattern data of the semiconductor device on the basis of the third design data when optical proximity correction is appropriately done for the third design data.   
     
     
         18 - 20 . (canceled)