Semiconductor Device Package Having Chip With Conductive Layer

Abstract

The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. The first electrical connecting element and the second electrical connecting element electrically connect the substrate to the chip. Therefore, the conductive layer of the chip has the effects of controlling the characteristic impedance and increasing the signal integrity.

1 . A semiconductor device package having a chip with a conductive layer, comprising:
 a substrate, having a first surface and a first circuit layer, wherein the first circuit layer is disposed adjacent to the first surface;   a chip, attached to the substrate and having a surface, at least one first pad, a plurality of second pads and a conductive layer, wherein the first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads;   at least one first electrical connecting element, electrically connecting the first circuit layer of the substrate to the first pad of the chip; and   at least one second electrical connecting element, electrically connecting the first circuit layer of the substrate to the conductive layer of the chip.   
     
     
         2 . The package as claimed in  claim 1 , wherein the substrate further has a window and a second surface, the window exposes the first pad and the second pads of the chip, and the surface of the chip is attached to the second surface of the substrate. 
     
     
         3 . The package as claimed in  claim 1 , wherein the substrate is a single-layered plate. 
     
     
         4 . The package as claimed in  claim 1 , wherein the substrate is a multi-layered plate. 
     
     
         5 . The package as claimed in  claim 1 , wherein the first pad of the chip is used to transmit input/output signals. 
     
     
         6 . The package as claimed in  claim 1 , wherein the conductive layer of the chip is a power/ground plane. 
     
     
         7 . The package as claimed in  claim 1 , wherein the chip further comprises a chip passivation disposed adjacent to the conductive layer. 
     
     
         8 . The package as claimed in  claim 1 , further comprising a molding compound encapsulating the substrate, the chip, the first electrical connecting element and the second electrical connecting element, wherein the chip is a wire-bonded chip. 
     
     
         9 . The package as claimed in  claim 8 , wherein the first circuit layer comprises a plurality of first fingers, the first electrical connecting element are a plurality of first wires which electrically connect the first fingers of the first circuit layer of the substrate to the first pad of the chip. 
     
     
         10 . The package as claimed in  claim 8 , wherein the first circuit layer comprises a plurality of second fingers, the second electrical connecting element are a plurality of second wires which electrically connect the second fingers of the first circuit layer of the substrate to the second pads of the chip. 
     
     
         11 . The package as claimed in  claim 8 , wherein the second electrical connecting element is a through via which penetrates through the substrate. 
     
     
         12 . The package as claimed in  claim 1 , wherein the chip is a flip chip. 
     
     
         13 . The package as claimed in  claim 12 , wherein the first electrical connecting element is a through via which penetrates through the substrate. 
     
     
         14 . The package as claimed in  claim 12 , wherein the second electrical connecting element is a through via which penetrates through the substrate. 
     
     
         15 . The package as claimed in  claim 1 , wherein the conductive layer is a plane having a large area, and the area of the conductive layer covers the second pads. 
     
     
         16 . The package as claimed in  claim 1 , further comprising a plurality of input/output solder balls, wherein the first circuit layer comprises a plurality of input/output pads disposed adjacent to the input/output pads. 
     
     
         17 . The package as claimed in  claim 1 , further comprising a plurality of power/ground solder balls, wherein the first circuit layer comprises a plurality of power/ground pads, the power/ground solder balls are disposed adjacent to the power/ground pads.