Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

Abstract

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

1 . A method of forming a chip, the method comprising:
 forming electronic circuitry on a first surface of a semiconductor wafer;   forming a trench having an interior surface in the first surface of the semiconductor concurrently with said forming electronic circuitry; and   depositing an electrically-conductive material within the trench to form an electrically-conductive via.   
     
     
         2 . The method of  claim 1 , wherein said forming a trench comprises forming the trench completely through the semiconductor wafer. 
     
     
         3 . The method of  claim 1 , further comprising forming a passivation layer over the first surface of the semiconductor wafer. 
     
     
         4 . The method of  claim 3 , wherein said forming a passivation layer comprises forming a dielectric layer on the interior surface of the trench. 
     
     
         5 . The method of  claim 3 , further comprising exposing a bond pad through the passivation layer. 
     
     
         6 . The method of  claim 5 , further comprising forming an electrically-conductive interconnect between the electrically-conductive via and the bond pad. 
     
     
         7 . The method of  claim 6 , further comprising backthinning the semiconductor wafer after said forming an electrically-conductive interconnect. 
     
     
         8 . The method of  claim 5 , wherein the bond pad is disposed on the first surface of the semiconductor wafer at a distance from the electrically-conductive via, and wherein the electrically-conductive interconnect extends along the first surface of the semiconductor wafer between the bond pad and the electrically-conductive via. 
     
     
         9 . The method of  claim 1 , wherein the electrically-conductive material comprises at least one of a doped polysilicon or a metal. 
     
     
         10 . The method of  claim 1 , further comprising stacking the chip on another chip and forming an element between the chip and the other chip, wherein the element is configured to provide thermal management for at least one of the chip or the other chip. 
     
     
         11 . The method of  claim 10 , wherein the element configured to provide thermal management comprises one of a thermally-conductive adhesive, a thermally-conductive epoxy, a micro-heat pipe structure, or an interleaved-copper thermal-management layer. 
     
     
         12 . The method of  claim 1 , further comprising removing a portion of a second surface of the semiconductor wafer to expose a plurality of grooves and the electrically-conductive material within the trench and to singulate the chip from another chip. 
     
     
         13 . A method comprising:
 forming electronic circuitry on a first surface of a semiconductor wafer to create a first semiconductor chip;   forming a trench in the first surface of the semiconductor wafer concurrently with said forming electronic circuitry;   depositing an electrically-conductive material within the trench to form an electrically-conductive via;   stacking a second semiconductor chip on the first semiconductor chip to form a stack of chips; and   forming, between the first and second semiconductor chips, an element configured to provide thermal management for at least one of the first or second semiconductor chips.   
     
     
         14 . The method of  claim 13 , further comprising forming a dielectric layer on an interior surface of the trench. 
     
     
         15 . The method of  claim 13 , wherein the element configured to provide thermal management comprises a thermally-conductive adhesive. 
     
     
         16 . The method of  claim 13 , wherein the element configured to provide thermal management comprises a thermally-conductive epoxy. 
     
     
         17 . The method of  claim 13 , wherein the element configured to provide thermal management comprises a micro-heat pipe structure. 
     
     
         18 . The method of  claim 13 , wherein the element configured to provide thermal management comprises an interleaved-copper thermal-management layer. 
     
     
         19 . The method of  claim 13 , further comprising forming a passivation layer over the first surface of the semiconductor wafer. 
     
     
         20 . The method of  claim 19 , further comprising exposing a bond pad through the passivation layer. 
     
     
         21 . The method of  claim 20 , further comprising forming an electrically-conductive interconnect between the electrically-conductive via and the bond pad. 
     
     
         22 . The method of  claim 21 , further comprising forming an electrically-conductive T-connect structure on a surface of the stack of chips, wherein the electrically-conductive T-connect structure is configured to electrically connect the electrically-conductive interconnect with an electrically-conductive bus on the surface of the stack of chips. 
     
     
         23 . The method of  claim 21 , further comprising backthinning the semiconductor wafer after said forming an electrically-conductive interconnect. 
     
     
         24 . The method of  claim 20 , wherein the bond pad is disposed on the first surface of the semiconductor wafer at a distance from the electrically-conductive via, and wherein the electrically-conductive interconnect extends along the first surface of the semiconductor wafer between the bond pad and the electrically-conductive via. 
     
     
         25 . The method of  claim 13 , wherein said stacking a second semiconductor chip on the first semiconductor chip comprises bonding the first and second semiconductor chips using a Z-conductive epoxy. 
     
     
         26 . The method of  claim 13 , further comprising removing a portion of a second surface of the semiconductor wafer to expose a plurality of grooves and the electrically-conductive material within the trench and to singulate the first semiconductor chip from the second semiconductor chip. 
     
     
         27 . A method comprising:
 forming electronic circuitry on a first surface of a semiconductor wafer;   forming a trench in the first surface of the semiconductor wafer concurrently with said forming electronic circuitry;   depositing an electrically-conductive material within the trench to form an electrically-conductive via;   forming a plurality of grooves into the first surface of the semiconductor wafer; and   removing a portion of a second surface of the semiconductor wafer to expose the plurality of grooves and the electrically-conductive material within the trench and to singulate a first semiconductor chip from a second semiconductor chip.   
     
     
         28 . The method of  claim 27 , further comprising releasably mounting the semiconductor wafer to a support plate. 
     
     
         29 . The method of  claim 27 , further comprising forming a dielectric layer on an interior surface of the trench. 
     
     
         30 . The method of  claim 27 , further comprising forming a passivation layer over the first surface of the semiconductor wafer. 
     
     
         31 . The method of  claim 30 , further comprising exposing a bond pad through the passivation layer. 
     
     
         32 . The method of  claim 31 , further comprising forming an electrically-conductive interconnect between the electrically-conductive via and the bond pad. 
     
     
         33 . The method of  claim 32 , further comprising backthinning the semiconductor wafer after said forming an electrically-conductive interconnect. 
     
     
         34 . The method of  claim 31 , wherein the bond pad is disposed on the first surface of the semiconductor wafer at a distance from the electrically-conductive via, and wherein the electrically-conductive interconnect extends along the first surface of the semiconductor wafer between the bond pad and the electrically-conductive via. 
     
     
         35 . The method of  claim 27 , wherein said forming a plurality of grooves comprises forming the plurality of grooves into the semiconductor wafer to a depth greater than a depth of the electronic circuitry. 
     
     
         36 . The method of  claim 27 , further comprising, prior to said removing a portion of a second surface of the semiconductor wafer, bonding the first surface of the semiconductor wafer to a substrate with a temporary releasable adhesive. 
     
     
         37 . The method of  claim 27 , further comprising stacking the first semiconductor chip on a second semiconductor chip and forming an element between the first semiconductor chip and the second semiconductor chip, wherein the element is configured to provide thermal management for at least one of the first or second semiconductor chips. 
     
     
         38 . The method of  claim 37 , wherein the element configured to provide thermal management comprises one of a thermally-conductive adhesive, a thermally-conductive epoxy, a micro-heat pipe structure, or an interleaved-copper thermal-management layer.