Resistance change memory

Abstract

A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

1 . A resistance change memory comprising:
 a first conductive line extending in a first direction;   a second conductive line extending in a second direction which is crossed to the first direction;   a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines; and   a control circuit which is connected to both of the first and second conductive lines,   wherein the control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly,   wherein the rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.   
     
     
         2 . The memory according to  claim 1 , wherein the diode is an SIS diode in which both the anode layer and the cathode layer are made of a semiconductor layer. 
     
     
         3 . The memory according to  claim 2 , wherein the insulating layer is one selected from the group of SiO 2 , SiN, Si 3 N 4 , Al 2 O 3 , SiON, HfO 2 , HfSiON, Ta 2 O 5 , TiO 2 , and SrTiO 3 . 
     
     
         4 . The memory according to  claim 2 , wherein the insulating layer includes one of an impurity atom, a semiconductor dot, and a metal dot, which form a defect level. 
     
     
         5 . The memory according to  claim 2 , wherein the semiconductor layer is one selected from the group of Si, SiGe, SiC, Ge, C, GaAs, oxide semiconductor, nitride semiconductor, carbide semiconductor, and sulfide semiconductor. 
     
     
         6 . The memory according to  claim 2 , wherein the anode layer is one of p-type Si, TiO 2 , ZrO 2 , InZnO x , ITO, SnO 2  containing Sb, ZnO containing Al, AgSbO 3 , InGaZnO 4 , and ZnO.SnO 2 , and the cathode layer is one of n-type Si, NiO x , ZnO, Rh 2 O 3 , ZnO containing N, and La 2 CuO 4 . 
     
     
         7 . The memory according to  claim 2 , wherein at least one of the anode layer and the cathode layer has an intrinsic semiconductor layer in a region being in contact with the insulating layer. 
     
     
         8 . The memory according to  claim 1 , wherein the diode is an MIS diode in which one of the anode layer and the cathode layer is made of a metal while the other is made of a semiconductor. 
     
     
         9 . The memory according to  claim 8 , wherein the insulating layer is one selected from the group of SiO 2 , SiN, Si 3 N 4 , Al 2 O 3 , SiON, HfO 2 , HfSiON, Ta 2 O 5 , TiO 2 , and SrTiO 3 . 
     
     
         10 . The memory according to  claim 8 , wherein the insulating layer includes one of an impurity atom, a semiconductor dot, and a metal dot, which form a defect level. 
     
     
         11 . The memory according to  claim 8 , wherein the metallic layer is made of one of A) a single element,
 B) compound metal that is an oxide, carbide, boride, nitride, or silicide, and C) TiN x , TiC x , TiB x , TiSi x , TaC x , TaB x , TaN x , WC x , WB x , W, WSi x , TaC x , TaB x , TaN x , TaSi x , HfSi x , Hf, YSi x , or ErSi x .   
     
     
         12 . The memory according to  claim 8 , wherein the semiconductor layer is one selected from the group of Si, SiGe, SiC, Ge, C, GaAs, oxide semiconductor, nitride semiconductor, carbide semiconductor, and sulfide semiconductor. 
     
     
         13 . The memory according to  claim 8 , wherein the semiconductor layer has an intrinsic semiconductor layer in a region being in contact with the insulating layer. 
     
     
         14 . The memory according to  claim 8 , wherein the anode layer is one of p-type Si, TiO 2 , ZrO 2 , InZnO x , ITO, SnO 2  containing Sb, ZnO containing Al, AgSbO 3 , InGaZnO 4 , and ZnO.SnO 2  when the semiconductor layer is the anode layer, and the cathode layer is one of n-type Si, NiO x , ZnO, Rh 2 O 3 , ZnO containing N, and La 2 CuO 4  when the semiconductor layer is the cathode layer. 
     
     
         15 . The memory according to  claim 8 , further comprising a semiconductor layer which is disposed on a side opposite to the insulating layer side of the metallic layer. 
     
     
         16 . The memory according to  claim 1 , wherein the diode is an MIM diode in which both the anode layer and the cathode layer are made of a metal. 
     
     
         17 . The memory according to  claim 16 , wherein the insulating layer is one selected from the group of SiO 2 , SiN, Si 3 N 4 , Al 2 O 3 , SiON, HfO 2 , HfSiON, Ta 2 O 5 , TiO 2 , and SrTiO 3 . 
     
     
         18 . The memory according to  claim 16 , wherein the insulating layer includes one of an impurity atom, a semiconductor dot, and a metal dot, which form a defect level. 
     
     
         19 . The memory according to  claim 16 , wherein the insulating layer comprises a first layer located on the anode layer side and a second layer located on the cathode layer side, and
 a barrier height of a material for the second layer differs from a barrier height of a material for the first layer.   
     
     
         20 . The memory according to  claim 16 , wherein the metallic layer is made of one of A) a single element, B) compound metal that is an oxide, carbide, boride, nitride, or silicide, and C) TiN x , TiC x , TiB x , TiSi x , TaC x , TaB x , TaN x , WC x , WB x , W, WSi x , TaC x , TaB x , TaN x , TaSi x , HfSi x , Hf, YSi x , or ErSi x .