Heterogeneous integration of low noise amplifiers with power amplifiers or switches

Abstract

A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.

1 . A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier, the transistor comprising:
 a substrate suitable for high electron mobility transistors and having a first region and a second region;   a first active layer deposited above the substrate;   an isolation implant deposited within the first region of the substrate, the isolation implant extending through the first active layer; and   a second active layer deposited above the isolation implant, the second active layer covering only the first region of the substrate.   
     
     
         2 . The transistor of  claim 1 , wherein the substrate is selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb). 
     
     
         3 . The transistor of  claim 1 , wherein the first active layer includes a pseudomorphic high electron mobility (PHEM) region. 
     
     
         4 . The transistor of  claim 1 , wherein the first active layer actuates the power amplifier or switch, and wherein the second active layer actuates the low noise amplifier. 
     
     
         5 . The transistor of  claim 4 , wherein the first active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer. 
     
     
         6 . The transistor of  claim 5 , further comprising a first buffer layer deposited between the first active layer and the substrate, the first buffer layer is formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof, wherein the isolated implant extends through the first buffer layer. 
     
     
         7 . The transistor of  claim 4 , wherein the second active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer. 
     
     
         8 . The transistor of  claim 7 , further comprising a second buffer layer deposited between the isolation implant and the second active layer, the second buffer layer is formed with Aluminum Gallium Antimonide (AlGaSb), wherein the second buffer layer and the first active layer define a well. 
     
     
         9 . The transistor of  claim 1 , wherein the first active layer actuates the low noise amplifier and the second active layer actuates the power amplifier or switch. 
     
     
         10 . The transistor of  claim 9 , wherein the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer. 
     
     
         11 . The transistor of  claim 10 , further comprising a first buffer layer deposited between the first active layer and the substrate, the first buffer layer is formed with Aluminum Gallium Antimonide (AlGaSb), wherein the isolated implant extends through the first buffer layer. 
     
     
         12 . The transistor of  claim 9 , wherein the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer. 
     
     
         13 . The transistor of  claim 12 , further comprising a second buffer layer deposited between the isolation implant and the second active layer, the second buffer layer is formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof, wherein the second buffer layer and the first active layer define a well. 
     
     
         14 . The transistor of  claim 1 , further comprising metal contacts deposited above the first and second active layers. 
     
     
         15 . A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier comprising:
 a substrate having a first region and a second region;   a first active layer deposited above the substrate;   an isolation implant deposited within the first region of the substrate, the isolation implant providing lateral isolation for the first active layer;   a second active layer deposited above the isolation implant, the second active layer configured to be substantially free from covering the first active layer; and   a plurality of metal contacts disposed on the first and second active layers.   
     
     
         16 . The transistor of  claim 15 , wherein the substrate is selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), and wherein the first active layer includes a pseudomorphic high electron mobility (PHEM) region. 
     
     
         17 . The transistor of  claim 15 , further comprising:
 a first buffer layer deposited between the first active layer and the substrate, such that the isolated implant extends through the first buffer layer; and   a second buffer layer deposited between the isolation implant and the second active layer, such that the second buffer layer and the first active layer define a well.   
     
     
         18 . The transistor of  claim 17 , wherein the first active layer actuates the power amplifier or switch, and wherein the second active layer actuates the low noise amplifier. 
     
     
         19 . The transistor of  claim 18 , wherein:
 the first active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer,   the first buffer layer is formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof,   the second active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer, and   the second buffer layer is formed with Aluminum Gallium Antimonide (AlGaSb).   
     
     
         20 . The transistor of  claim 17 , wherein the first active layer actuates the low noise amplifier and the second active layer actuates the power amplifier or switch. 
     
     
         21 . The transistor of  claim 20 , wherein:
 the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer,   the first buffer layer is formed with Aluminum Gallium Antimonide (AlGaSb), wherein the isolated implant extends through the first buffer layer,   the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer, and   the second buffer layer is formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof.   
     
     
         22 . A method for heterogeneously integrating a power amplifier or switch with a low-noise amplifier, comprising the steps of:
 depositing a first active layer above a substrate suitable for high electron mobility transistors;   implanting ions in a first region of the first active layer to form an isolation implant;   depositing a second active layer above the isolation implant; and   depositing metal contacts on the second active layer and on a second region of the first active layer.   
     
     
         23 . The method of  claim 22 , wherein the substrate is selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb). 
     
     
         24 . The method of  claim 22 , further comprising depositing a first buffer layer on the substrate before depositing the first active layer. 
     
     
         25 . The method of  claim 22 , further comprising depositing a second buffer layer on the isolation implant and substantially within the first region of the first active layer. 
     
     
         26 . The method of  claim 22 , wherein the first active layer actuates the power amplifier or switch, and the second active layer activates the low noise amplifier. 
     
     
         27 . The method of  claim 26 , further comprising:
 depositing a first buffer layer on the substrate before depositing the first active layer, the first buffer layer formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof; and   depositing a second buffer layer on isolation implant and substantially within the first region of the first active layer, the second buffer layer formed with Aluminum Gallium Antimonide (AlGaSb),   wherein the first active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer, and   wherein the second active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.   
     
     
         28 . The method of  claim 22 , wherein the second active layer actuates the power amplifier or switch, and the first active layer activates the low noise amplifier. 
     
     
         29 . The method of  claim 28 , further comprising:
 depositing a first buffer layer on the substrate before depositing the first active layer, the first buffer layer formed with Aluminum Gallium Antimonide (AlGaSb); and   depositing a second buffer layer on isolation implant and substantially within the first region of the first active layer, the second buffer layer formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof,   wherein the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer, and   wherein the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.