Metal gate transistor and method for fabricating the same

Abstract

A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.

1 . A metal gate transistor, comprising:
 a substrate;   a metal gate disposed on the substrate, comprising:
 a high-k dielectric layer; 
 a U-shaped cap layer disposed over a surface of the high-k dielectric layer for adjusting the work function of the metal gate transistor, wherein the U-shaped cap layer comprises LaO, Dy 2 O 3 , or other lanthanide oxides; 
 a U-shaped metal layer disposed over the U-shaped cap layer; and 
   a source/drain region disposed in the substrate with respect to two sides of the metal gate.   
     
     
         2 . The metal gate transistor of  claim 1 , wherein the metal gate transistor is a NMOS transistor. 
     
     
         3 . The metal gate transistor of  claim 1 , wherein the U-shaped metal layer comprises TiN, TaC, Ta, TaSiN, Al, or TiAlN. 
     
     
         4 . The metal gate transistor of  claim 1 , wherein the high-k dielectric layer is U-shaped. 
     
     
         5 . The metal gate transistor of  claim 1 , further comprising a conductive layer disposed on the U-shaped metal layer. 
     
     
         6 . The metal gate transistor of  claim 5 , wherein the conductive layer comprises Al, W, TiAl or CoWP. 
     
     
         7 . A metal gate transistor, comprising:
 a substrate;   a first metal gate transistor having a first metal gate disposed on the substrate, wherein the first metal gate comprises:
 a first U-shaped high-k dielectric layer; 
 a U-shaped cap layer; and 
 a first U-shaped metal layer; 
   a first source/drain region disposed in the substrate adjacent to two sides of the first metal gate;   a second metal gate transistor having a second metal gate disposed on the substrate, wherein the second metal gate comprises:
 a second U-shaped high-k dielectric layer; and 
 a second U-shaped metal layer; and 
   a second source/drain region disposed in the substrate adjacent to two sides of the second metal gate.   
     
     
         8 . The metal gate transistor of  claim 7 , wherein the first metal gate transistor is a NMOS transistor. 
     
     
         9 . The metal gate transistor of  claim 7 , wherein the second metal gate transistor is a PMOS transistor. 
     
     
         10 . The metal gate transistor of  claim 7 , wherein the U-shaped cap layer comprises LaO, MgO, Dy 2 O 3 , or other lanthanide oxides. 
     
     
         11 . The metal gate transistor of  claim 7 , wherein the first U-shaped high-k dielectric layer and the second U-shaped high-k dielectric layer comprise HfSiO, HfSiON, HfO, LaO, LaA 10 , ZrO, ZrSiO, or HfZrO. 
     
     
         12 . The metal gate transistor of  claim 7 , wherein the first U-shaped metal layer and the second U-shaped metal layer comprise TiN, TaC, Ta, TaSiN, Al, or TiAlN. 
     
     
         13 . The metal gate transistor of  claim 7 , further comprising a conductive layer disposed on the first U-shaped metal layer and the second U-shaped metal layer. 
     
     
         14 . The metal gate transistor of  claim 13 , wherein the conductive layer comprises Al, W, TiAl or CoWP.