Semiconductor memory

Abstract

A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.

1 . A semiconductor memory comprising:
 active areas; and   the element isolation areas which isolate the active areas,   wherein the element isolation areas have an element isolation insulating film,   the element isolation areas have first element isolation areas, a second element isolation area and a third element isolation area,   the first isolation areas are narrower than the second and third element isolation areas,   the second element isolation area is adjacent to one of the first element isolation areas via one of the active areas,   the third element isolation area is adjacent to one of the second element isolation areas via another one of the active areas, and   the third element isolation area has a step.   
     
     
         2 . The semiconductor memory according to  claim 1  further comprising:
 a gate electrode disposed on each of the active areas, and 
 an inter-electrode insulating film disposed on the element isolation areas and gate electrode, 
 wherein the inter-electrode insulating film contacts a top face of the step. 
 
     
     
         3 . The semiconductor memory according to  claim 2  further comprising:
 a first gate insulating film disposed on first ones of the active areas located between the first element isolation areas, and 
 a second gate insulating film disposed on second ones of the active areas located between the one of first element isolation area and the second element isolation area, 
 wherein the second gate insulating film is thicker than the first gate insulating film. 
 
     
     
         4 . The semiconductor memory according to  claim 2  wherein,
 a top face of the gate electrode is higher than a top face of the element isolation insulating film in the first and second element isolation areas, and 
 a top face of the gate electrode is at the same level as a part of a top face of the element isolation insulating film in the third element isolation area. 
 
     
     
         5 . The semiconductor memory according to  claim 1 , wherein
 a width of the active areas located between the first element isolation areas is equal to a width of the active area located between the one of the first element isolation areas and the second element isolation area.   
     
     
         6 . A semiconductor memory comprising:
 active areas; and   element isolation areas which isolate the active areas,   wherein the element isolation areas have an element isolation insulating film,   the element isolation areas have first element isolation areas, a second element isolation area and a third element isolation area,   the first isolation areas are narrower than the second and third element isolation areas,   the second element isolation area is adjacent to one of the first element isolation areas via an one of the active areas,   the third element isolation area is adjacent to the second element isolation areas via another one of the active areas, and   the second element isolation area has a step.   
     
     
         7 . The semiconductor memory according to  claim 6  further comprising:
 a gate electrode disposed on each of the active areas, 
 an inter-electrode insulating film disposed on the element isolation areas and the gate electrode, 
 wherein the inter-electrode insulating film contacts a top face of the step. 
 
     
     
         8 . The semiconductor memory according to  claim 6  further comprising:
 a first gate insulating film disposed on first ones of the active areas located between the first element isolation areas, 
 a second gate insulating film disposed on second ones of the active areas located between the one first element isolation area and the second element isolation area, 
 wherein the second gate insulating film is thicker than the first gate insulating film. 
 
     
     
         9 . The semiconductor memory according to  claim 7  wherein,
 a top face of the gate electrode is higher than a top face of the element isolation insulating film in the first and second element isolation areas, and 
 a top face of the gate electrode is at the same level as part of a top face of the element isolation insulating film in the third element isolation area. 
 
     
     
         10 . The semiconductor memory according to  claim 6 , wherein
 a width of the active areas located between the first element isolation areas is equal to a width of the active area located between the one first element isolation area and the second element isolation area.