Chip package and manufacturing method thereof

Abstract

An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

1 . A chip package, comprising:
 a substrate;   a first cavity extending downward from an upper surface of the substrate;   a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the first cavity;   a first chip having a first upper surface and disposed overlying the metal layer in the first cavity, wherein the first upper surface is not lower than an upper surface of the metal layer outside of the first cavity; and   a protective layer covering the first chip.   
     
     
         2 . The chip package as claimed in  claim 1 , further comprising at least a first conducting structure overlying the protective layer and electrically connected to the first chip or the metal layer. 
     
     
         3 . The chip package as claimed in  claim 1 , wherein the sidewall of the first cavity inclines to the upper surface of the substrate. 
     
     
         4 . The chip package as claimed in  claim 1 , further comprising a first insulating layer located between the metal layer and the protective layer, wherein an upper surface of the first insulating layer is not higher than the first upper surface of the first chip. 
     
     
         5 . The chip package as claimed in  claim 1 , further comprising:
 a second cavity extending downward from the first surface, wherein the metal layer conformally covers a sidewall and a bottom portion of the second cavity; and   a second chip having a second upper surface and disposed overlying the metal layer in the second cavity, wherein the second upper surface is not lower than the upper surface of the metal layer outside of the second cavity.   
     
     
         6 . The chip package as claimed in  claim 5 , further comprising at least a second conducting structure disposed overlying the protective layer and electrically connected to the second chip or the metal layer. 
     
     
         7 . A method of forming a chip package, comprising:
 providing a temporary substrate;   forming a first soft insulating layer overlying the temporary substrate;   bonding at least one chip overlying the first soft insulating layer;   hardening the first soft insulating layer to form a first insulating layer;   forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the first insulating layer and the chip;   forming a dielectric layer overlying the metal layer;   removing the temporary substrate;   removing the first insulating layer; and   forming a protective layer overlying the chip.   
     
     
         8 . The method of forming a chip package as claimed in  claim 7 , wherein the bonding of the chip comprises pressing the chip such that a portion of the chip penetrates into the first soft insulating layer. 
     
     
         9 . The method of forming a chip package as claimed in  claim 7 , wherein a sidewall of the chip inclines to an upper surface of the temporary substrate. 
     
     
         10 . The method of forming a chip package as claimed in  claim 7 , further comprising forming a second soft insulating layer overlying the temporary substrate before the forming of the first soft insulating layer. 
     
     
         11 . The method of forming a chip package as claimed in  claim 10 , wherein the step of bonding the chip overlying the first soft insulating layer comprises pressing the chip such that a portion of the chip penetrates into the first soft insulating layer and directly contacts with the second soft insulating layer. 
     
     
         12 . The method of forming a chip package as claimed in  claim 11 , further comprising hardening the second soft insulating layer to form a second insulating layer. 
     
     
         13 . The method of forming a chip package as claimed in  claim 12 , wherein the hardening of the second soft insulating layer and the hardening of the first soft insulating layer are performed simultaneously. 
     
     
         14 . The method of forming a chip package as claimed in  claim 10 , further comprising hardening the second soft insulating layer to form a second insulating layer before the forming the first insulating layer. 
     
     
         15 . The method of forming a chip package as claimed in  claim 14 , wherein the bonding of the chip comprises pressing the chip such that a portion of the chip penetrates into the first soft insulating layer and directly contacts with the second insulating layer. 
     
     
         16 . A method of forming a chip package, comprising:
 providing a temporary substrate;   forming an insulating layer overlying the temporary substrate;   forming a soft insulating layer overlying the insulating layer;   bonding at least one chip overlying the soft insulating layer;   forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the soft insulating layer and the chip;   forming a dielectric layer overlying the metal layer;   removing the temporary substrate;   removing the soft insulating layer; and   forming a protective layer overlying the chip.   
     
     
         17 . The method of forming a chip package as claimed in  claim 16 , wherein the bonding of the chip comprises pressing the chip such that a portion of the chip penetrates into the soft insulating layer. 
     
     
         18 . The method of forming a chip package as claimed in  claim 17 , wherein the chip directly contacts with the insulating layer. 
     
     
         19 . The method of forming a chip package as claimed in  claim 16 , wherein the forming of the insulating layer comprises forming a second soft insulating layer overlying the temporary substrate and hardening the second soft insulating layer to form the insulating layer. 
     
     
         20 . The method of forming a chip package as claimed in  claim 16 , further comprising a plurality of conducting structures overlying the protective layer, wherein the conducting structures electrically connect the chip or the metal layer.