Inventor · disambiguated record
Baw-Ching Perng
Also filed as: PERNG BAW-CHING
32 granted patents·4 pending applications·968 citations·filing 2002–2017
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG24PERNG BAW-CHING3XINTEC INC3GRAND PLASTIC TECHNOLOGY CORP1JCET SEMICONDUCTOR SHAOXING CO LTD1
Top patents by PatentIndex Score
36 records- 0198US7354847B2Method of trimming technologyTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Apr 8, 2008·528 cites·37 claims
- 0295US7176137B2Method for multiple spacer width controlTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Feb 13, 2007·101 cites·20 claims
- 0390US9673093B2Semiconductor device and method of making wafer level chip scale packageSTATS CHIPPAC LTD·Filed 2014·Granted Jun 6, 2017·9 cites·26 claims
- 0488US7012027B2Zirconium oxide and hafnium oxide etching using halogen containing chemicalsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Mar 14, 2006·44 cites·14 claims
- 0587US6498067B1Integrated approach for controlling top dielectric loss during spacer etchingTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Dec 24, 2002·51 cites·26 claims
- 0683US6943077B2Selective spacer layer deposition method for forming spacers with different widthsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Sep 13, 2005·24 cites·21 claims
- 0782US7172933B2Recessed polysilicon gate structure for a strained silicon MOSFET deviceTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Feb 6, 2007·34 cites·14 claims
- 0881US7230270B2Self-aligned double gate device and method for forming sameTAIWAN SEMICONDUCTOR MANFACTUR·Filed 2004·Granted Jun 12, 2007·27 cites·28 claims
- 0976US11676938B2Semiconductor device and method of making wafer level chip scale packageJCET SEMICONDUCTOR SHAOXING CO LTD·Filed 2017·Granted Jun 13, 2023·2 cites·12 claims
- 1075US7122484B2Process for removing organic materials during formation of a metal interconnectTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 17, 2006·19 cites·31 claims
- 1174US7081413B2Method and structure for ultra narrow gateTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jul 25, 2006·16 cites·16 claims
- 1273US6746900B1Method for forming a semiconductor device having high-K gate dielectric materialTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jun 8, 2004·17 cites·25 claims
- 1371US8053894B2Surface treatment of metal interconnect linesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Nov 8, 2011·3 cites·24 claims
- 1470US7378308B2CMOS devices with improved gap-fillingTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted May 27, 2008·4 cites·12 claims
- 1570US6955984B2Surface treatment of metal interconnect linesTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Oct 18, 2005·12 cites·34 claims
- 1669US8610271B2Chip package and manufacturing method thereofPERNG BAW-CHING·Filed 2010·Granted Dec 17, 2013·2 cites·13 claims
- 1769US8564133B2Chip package and method for forming the sameWEN YING-NAN·Filed 2010·Granted Oct 22, 2013·3 cites·22 claims
- 1868US7148114B2Process for patterning high-k dielectric materialTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Dec 12, 2006·2 cites·20 claims
- 1968US7115526B2Method for wet etching of high k thin film at low temperatureGRAND PLASTIC TECHNOLOGY CORP·Filed 2002·Granted Oct 3, 2006·15 cites·23 claims
- 2065US6479403B1Method to pattern polysilicon gates with high-k material gate dielectricTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 12, 2002·15 cites·50 claims
- 2164US7037849B2Process for patterning high-k dielectric materialTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted May 2, 2006·7 cites·19 claims
- 2263US8410599B2Power MOSFET packagePERNG BAW-CHING·Filed 2010·Granted Apr 2, 2013·2 cites·10 claims
- 2363US7271103B2Surface treated low-k dielectric as diffusion barrier for copper metallizationTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Sep 18, 2007·8 cites·12 claims
- 2461US6838381B2Methods for improving sheet resistance of silicide layer after removal of etch stop layerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jan 4, 2005·11 cites·25 claims
- 2561US6812044B2Advanced control for plasma processTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 2, 2004·7 cites·11 claims
- 2654US9093450B2Chip package and manufacturing method thereofXINTEC INC·Filed 2013·Granted Jul 28, 2015·0 cites·11 claims
- 2754US8916420B2Chip package and manufacturing method thereofXINTEC INC·Filed 2013·Granted Dec 23, 2014·0 cites·14 claims
- 2854US6969688B2Wet etchant composition and method for etching HfO2 and ZrO2TAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 29, 2005·5 cites·11 claims
- 2949US8766431B2Power MOSFET packageXINTEC INC·Filed 2013·Granted Jul 1, 2014·0 cites·10 claims
- 3048US2006113616A1Selective spacer layer deposition method for forming spacers with different widthsLIU AI-SEN·Filed 2005·Application pending·0 cites
- 3145US7400401B2Measuring low dielectric constant film properties during processingTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jul 15, 2008·0 cites·17 claims
- 3244US2006054597A1Wet etchant composition and method for etching HfO2 and ZrO2TAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 3343US2011024894A1Chip package and manufacturing method thereofPERNG BAW-CHING·Filed 2010·Application pending·0 cites
- 3441US7208331B2Methods and structures for critical dimension and profile measurementTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Apr 24, 2007·0 cites·6 claims
- 3540US2005274393A1Wafer clean processTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3635US7011929B2Method for forming multiple spacer widthsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Mar 14, 2006·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →