Substrate structure for cavity package

Abstract

Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure.

1 . A semiconductor device comprising:
 a multilayer base substrate comprising a base center portion surrounded by a peripheral portion, wherein a base interconnect via is disposed in the peripheral portion;   a top substrate disposed over the multilayer base substrate having an open cavity matching the base center portion, wherein a through-hole interconnect via is disposed through the top substrate;   a top conductive bump disposed over the top substrate for receiving a semiconductor package; and   a bottom conductive bump attached to the multilayer base substrate and aligned with the top conductive bump along an alignment line;
 wherein the top conductive bump, the through-hole interconnect via, the base interconnect via, and the bottom conductive bump are electrically interconnected; and either the through-hole interconnect via or the base interconnect via is disposed offset from the alignment line between the top and bottom conductive bumps. 
   
     
     
         2 . The device of  claim 1 , further comprising at least one semiconductor die attached to the base center portion in the open cavity; and a molding compound to encapsulate the at least one semiconductor die and to fill the open cavity. 
     
     
         3 . The device of  claim 2 , wherein the at least one semiconductor die is a flip chip die or a wire-bonded die. 
     
     
         4 . The device of  claim 2 , wherein the at least one semiconductor die is one of a microprocessor, a digital signal processor, a radio frequency chip, a memory, a microcontroller, a system-on-a-chip or a combination thereof. 
     
     
         5 . The device of  claim 1 , wherein the one of the through-hole interconnect via and the base interconnect via is offset at least about  20  microns from the alignment line. 
     
     
         6 . The device of  claim 1 , further comprising a plurality of top conductive bumps, a plurality of through-hole interconnect vias, a plurality of base interconnect vias, and a plurality of bottom conductive bumps with each corresponding top conductive bump, through-hole interconnect via, base interconnect via, and bottom conductive bump electrically interconnected. 
     
     
         7 . The device of  claim 6 , wherein the plurality of top conductive bumps or the plurality of bottom conductive bumps has a pitch ranging from about 0.4 mm to about 0.65 mm. 
     
     
         8 . The device of  claim 7 , wherein the one of the through-hole interconnect via and the base interconnect via is offset from the alignment line for less than a half of the pitch of the plurality of top conductive pumps 
     
     
         9 . The device of  claim 1 , wherein the top substrate includes at least one metal layer. 
     
     
         10 . The device of  claim 1 , wherein each of the top and bottom conductive bumps comprises a solder ball. 
     
     
         11 . The device of  claim 1 , wherein the multilayer base substrate is an organic substrate, a ceramic substrate, a glass epoxy substrate, or a bismaleimide triazine (BT) substrate. 
     
     
         12 . A method for forming a semiconductor device comprising:
 providing a multilayer base laminate substrate comprising a base center portion surrounded by a peripheral portion that includes a plurality of base interconnect vias, wherein the base center portion is capable of mounting at least one die;   providing a top substrate comprising an open cavity and a plurality of through-holes in the top substrate;   bonding the top substrate to the multilayer base laminate substrate such that the open cavity matches the base center portion, and each through-hole of the top substrate is not aligned with a corresponding base interconnect via of the multilayer base laminate substrate;   filling each through-hole of the top substrate with a metal to form a plurality of top interconnect vias;   assembling at least one die on the base center portion in the open cavity; and   mounting a top package on the top substrate through a plurality of top conductive bumps to form a package-on-package structure.   
     
     
         13 . The method of  claim 12 , further comprising an adhesive coupling for bonding the top substrate and the multilayer base laminate substrate. 
     
     
         14 . The method of  claim 12 , further comprising forming a plurality of contact pads on the multilayer base laminate substrate, wherein each contact pad connects to a corresponding through-hole in the top substrate during the bonding. 
     
     
         15 . The method of  claim 12 , wherein the formation of the plurality of top interconnect vias further comprises plating a wall of each through-hole in the top substrate with a copper and filling the plated through-hole with a metal paste. 
     
     
         16 . The method of  claim 12 , wherein the metal used to form the plurality of top interconnect vias comprises Pb, Sn, In, Ag, Au, Cu, Ni or a combination thereof. 
     
     
         17 . The method of  claim 12 , wherein the assembly of at least one die on the base center portion comprises one of a flip chip type and a wire bond type interconnection. 
     
     
         18 . The method of  claim 12 , further comprising filling the open cavity by a molding compound to encapsulate the assembled at least one die. 
     
     
         19 . The method of  claim 12 , further comprising attaching a printed circuit board to the multilayer base laminate substrate through a plurality of bottom conductive bumps each aligned with a corresponding top conductive bump. 
     
     
         20 . A semiconductor device comprising:
 a cavity substrate structure comprising a bottom solder ball attached on a backside, and a top solder ball attached on a front side and aligned with the bottom solder ball to form an alignment line; wherein the cavity substrate structure comprises:
 a multilayer base laminate substrate having a base center portion surrounded by a peripheral portion that further comprises a base interconnect via, 
 a top substrate disposed over the multilayer base laminate substrate having an open cavity matching the base center portion, wherein the top substrate comprises a through-hole interconnect via, and wherein the top solder ball, the through-hole interconnect via, the base interconnect via, and the bottom solder ball are electrically interconnected; and one of the through-hole interconnect via and the base interconnect via is offset from the alignment line; 
   at least one semiconductor die attached on the base center portion in the open cavity of the cavity substrate structure; and   a top package disposed over the cavity substrate structure by the top solder ball.