Schottky barrier diode (sbd) and its off-shoot merged pn/schottky diode or junction barrier schottky (jbs) diode

Abstract

A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid may make electrical contact to the Schottky bather metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.

1 . A semiconductor device comprising a layer of a first semiconductor type and a central active area formed in the layer, wherein the central active area further comprises:
 a plurality of spaced-apart embedded wells of a second semiconductor type;   a peripheral region of the second semiconductor type surrounding the plurality of embedded wells; and   a metal structure located on an upper surface of the layer; wherein:   the embedded wells are spaced below the upper surface of the layer, and the metal structure contacts and forms a first Schottky barrier contact with the layer of the first semiconductor type spaced above the embedded wells; and   the metal structure makes direct contact to the peripheral region of the second semiconductor type;   wherein the embedded wells are formed as an array of stripes that have a lateral width of around 1 to 3 microns and are spaced apart from each other laterally by around 4 to 8 microns.   
     
     
         2 . The semiconductor device of  claim 1  wherein the peripheral region is surrounded by a series of spaced floating guard rings of the second semiconductor type isolated from the metal structure by a passivation layer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the embedded wells include a p-type dopant implanted at a dose of around 1×10 13  cm −2  to 6×10 15  cm −2  and an energy of around 170 KeV to 400 KeV. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the layer comprises a shallow epitaxially deposited or implanted surface layer of the first conductive type over the embedded wells. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the layer comprises silicon carbide. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the first conductivity type is n-type and the second conductivity type is p-type. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the embedded wells include a p-type dopant implanted at a dose of around 1×10 13  cm −2  to 6×10 15  cm −2  and an energy of around 170 KeV to 400 KeV.