Substrate comprising different types of surfaces and method for obtaining such substrates

Abstract

A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

1 . A semiconductor structure useful for the fabrication of semiconductor devices comprising:
 a support having a front face and crystalline defects with a size greater than 10 nm at a density greater than 10 3 /cm 3 ;   an insulating layer disposed on a first region of the front face of the support;   a superficial layer disposed on the insulating layer and having an exposed surface; and   an additional layer disposed at least on a second region of the front face of the support, the additional layer having an exposed surface and a thickness sufficient to bury the crystalline defects of the support.   
     
     
         2 . The structure of  claim 1  wherein the additional layer has a thickness greater than 0.1 micron. 
     
     
         3 . The structure of  claim 1  further comprising an epitaxial layer arranged on at least the first region of the front face of the support and between the support and the insulating layer. 
     
     
         4 . The structure of  claim 3  wherein the epitaxial layer has a thickness greater than 0.1 micron. 
     
     
         5 . The structure of  claim 1  wherein the exposed surface of the additional layer is not coplanar with the exposed surface of the superficial layer. 
     
     
         6 . The structure of  claim 1  wherein the exposed surface of the additional layer and the exposed surface of the superficial layer are offset by less than 100 nm. 
     
     
         7 . The structure of  claim 1  wherein the additional layer has one crystalline orientation, and wherein the superficial layer has a different crystalline orientation. 
     
     
         8 . The structure of  claim 1  wherein the additional layer and the superficial layer comprise different materials. 
     
     
         9 . A method of manufacturing a semiconductor structure useful for the fabrication of semiconductor devices comprising:
 providing a substrate comprising a support, a continuous insulating layer disposed on a front face of the support, and a superficial layer disposed on the insulating layer;   forming a masking layer on a first region of the superficial layer;   removing the superficial layer and the insulating layer in a second region not covered by the masking layer;   forming an additional layer in the second region; and   planarizing the additional layer.   
     
     
         10 . The method of  claim 9  wherein the thickness of the additional layer is greater than a combined thickness of the superficial layer, the insulating layer, and the masking layer. 
     
     
         11 . The method of  claim 9  wherein planarizing of the additional layer is terminated at the masking layer. 
     
     
         12 . The method of  claim 9  wherein the masking layer comprises an oxide material with a thickness between 10 nm and 50 nm. 
     
     
         13 . The method of  claim 9  further comprising, before planarizing, removing an upper layer of the masking layer so as to leave a remaining lower layer of the masking layer, and wherein the planarizing of the additional layer is terminated at the remaining lower layer. 
     
     
         14 . The method of  claim 13  wherein the upper layer comprises a nitride material and the lower layer comprises an oxide material. 
     
     
         15 . The method of  claim 9  further comprising, before forming the additional layer, forming an insulator spacer for sealing laterally the superficial layer and the insulating layer. 
     
     
         16 . The method of  claim 9  wherein the support comprises crystalline defects, and wherein the additional layer has a sufficient thickness to bury the crystalline defects present in the support. 
     
     
         17 . The method of  claim 9  further comprising forming at the same time electronic devices in the additional layer and in the superficial layer. 
     
     
         18 . The method of  claim 17  further comprising:
 performing a single lithographic exposure on the exposed surface of the second region and on the exposed surface of the superficial layer by use of an image forming apparatus, wherein both exposed surfaces are within a first depth of focus of the image forming apparatus corresponding to a first predetermined image resolution so that the exposures on both surfaces are within the first predetermined image resolution; 
 performing a single etching step of both exposed surfaces; and 
 performing a single implantation step into both exposed surfaces. 
 
     
     
         19 . The method of  claim 18  wherein a selected one of the exposed surface is within a second depth of focus corresponding to a second higher predetermined image resolution, and wherein the first depth of focus overlaps the second depth of focus so that the selected surface is within the second depth of focus while the other surface is within the first depth of focus. 
     
     
         20 . The method according of  claim 17  further comprising:
 performing a first distinct lithographic exposure on an exposed surface of the second region; 
 performing a second distinct lithographic exposure on an exposed surface of the superficial layer; 
 performing a single etching step of both exposed surfaces; and 
 performing a single implantation step into both exposed surfaces.