Trenched mosfets with part of the device formed on a (110) crystal plane

Abstract

This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

1 . A trenched semiconductor power device comprising a gate disposed in a trench formed in a semiconductor substrate wherein:
 said trench further comprising sidewalls formed along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel along said first crystal orientation disposed near said sidewalls in an active cell region of said substrate and said trench further comprising a trench bottom surface formed along a second crystal orientation different from said first crystal orientation of said semiconductor substrate and said trench further comprising a single thermally grown gate oxide layer covering said sidewalls and simultaneously covering said bottom surface having a substantially same gate oxide thickness.   
     
     
         2 . The trenched semiconductor power device of  claim 1  wherein:
 said semiconductor power device is a P-channel MOSFET power device and said sidewalls formed along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility along a P-channel along said (110) crystal orientation whereby said P-channel MOSFET power device having a reduced on-resistance. 
 
     
     
         3 . The trenched semiconductor power device of  claim 1  wherein:
 said sidewalls of said trench formed along a (110) crystal orientation and said bottom surface of said trench having a round-shaped surface with an enhanced thermal oxide growth rate and formed along a (100) crystal orientation of said semiconductor substrate wherein said round-shaped bottom surface is covered with a thermally grown single gate oxide layer substantially of same thickness as a gate oxide layer covering said sidewalls. 
 
     
     
         4 . The trenched semiconductor power device of  claim 2  wherein:
 said sidewalls and said bottom surface of said trench are covered with an annealed single gate oxide layer having substantially a same gate oxide layer thickness. 
 
     
     
         5 . A trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate wherein:
 said trench further comprising sidewalls formed along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate along said first crystal orientation and a trench bottom surface formed along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and   said trench further comprising a single dielectric layer having different thickness formation rates on said sidewalls and said trench bottom covering said sidewalls having a substantially a same thickness as a simultaneously formed single dielectric layer covering said bottom surface of said trench.   
     
     
         6 . The trenched MOSFET power transistor of  claim 5  wherein:
 said sidewalls are formed along a (110) crystal orientation and said bottom surface is formed along a (100) crystal orientation wherein said single dielectric layer having a higher thickness formation rate on said sidewalls than said simultaneously formed single dielectric layer on said bottom surface. 
 
     
     
         7 . The trenched MOSFET power transistor of  claim 5  wherein:
 said MOSFET power transistor is a P-channel MOSFET power transistor and said sidewalls are formed along a (110) crystal orientation with an enhanced P-carrier mobility along said (110) crystal orientation and said bottom surface is formed along a (100) crystal orientation. 
 
     
     
         8 . The trenched MOSFET power transistor of  claim 5  wherein:
 at least one of sidewalls is formed along a (100) crystal orientation having a round sidewall surface to improve a dielectric thickness formation rate thereon and said bottom surface is formed along a (110) crystal orientation wherein said dielectric layer having a lower thickness formation rate on a surface along a (100) crystal orientation than a thickness formation rate on a (110) crystal orientation. 
 
     
     
         9 . An N-channel trenched MOSFET power transistor includes a trenched gate disposed in a trench wherein:
 sidewalls of said trench are formed along a (100) crystal orientation and a trench bottom surface is formed along a (110) crystal orientation both covered by a single thermally grown dielectric layer wherein said dielectric layer on said bottom surface is slightly thicker than said dielectric layer on said sidewall surface for reducing a gate-to-drain capacitance.   
     
     
         10 . The trenched MOSFET power transistor of  claim 5  wherein:
 said single thermally grown dielectric layer is an oxide layer having substantially a same thickness covering said sidewalls and said bottom surface of said trench wherein said single thermally grown oxide layer having a higher thickness formation rate on said sidewalls than on said bottom surface. 
 
     
     
         11 . A trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate wherein:
 said trench disposed in an active cell area further comprising two sidewalls formed along a first crystal orientation with an enhanced carrier mobility along said first crystal orientation and two other sidewalls formed along a second crystal orientation of said semiconductor substrate and a trench bottom surface formed along said second crystal orientation different from said first crystal orientation of said semiconductor substrate; and   said trench further comprising a single dielectric layer covering said sidewalls having a substantially same thickness as a simultaneously formed single dielectric layer covering said bottom surface of said trench.   
     
     
         12 . The trenched MOSFET power transistor of  claim 11  wherein:
 said MOSFET power transistor is a P-channel MOSFET power transistor having an enhanced P-type carrier mobility along a channel formed near said sidewalls of (110) crystal orientation whereby said P-channel MOSFET power transistor having a reduced on-resistance. 
 
     
     
         13 . The trenched MOSFET power transistor of  claim 11  wherein:
 said dielectric layer is a single thermally grown oxide layer having substantially a same thickness covering said sidewalls and said bottom surface of said trench wherein two of said sidewalls formed along said second crystal orientation having a round sidewall surface for improving a formation rate of said single thermally grown oxide layer thereon in order to form said single thermally grown oxide layer to have said substantially a same thickness covering said two sidewalls formed along said first crystal orientation. 
 
     
     
         14 . A trenched MOSFET power transistor comprising a gate disposed in a trench formed in an active cell area of a semiconductor substrate wherein:
 said trench constituting an elongated stripe further comprising sidewalls along an elongated direction formed along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor with an enhanced carrier mobility along said first crystal orientation and a trench termination end surface at terminal ends of said elongated stripe along a second crystal orientation of said semiconductor substrate different from said first crystal orientation wherein said termination having a end surface having a different surface shape for providing a different dielectric layer formation rate thereon.   
     
     
         15 . The trenched MOSFET power transistor of  claim 14  wherein
 said termination end surface having a curved surface with said enhanced dielectric layer formation rate along said second crystal orientation of said semiconductor substrate whereby device performance improvements along said sidewalls formed in said first crystal orientation along said elongated direction may be increased and device performance differences arising from said second crystal orientation on said termination end surface are reduced. 
 
     
     
         16 . The trenched MOSFET power transistor of  claim 14  wherein:
 said sidewall are formed along a (110) crystal orientation and said termination end surface is formed along a (100) crystal orientation. 
 
     
     
         17 . The trenched MOSFET power transistor of  claim 14  wherein:
 said MOSFET power transistor is a P-channel MOSFET power transistor and said sidewalls formed along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility along a channel aligned in said (110) crystal orientation whereby said P-channel MOSFET power device having a reduced on-resistance. 
 
     
     
         18 . The trenched MOSFET power transistor of  claim 14  wherein:
 said MOSFET power transistor is a N-channel MOSFET power transistor and said sidewalls along said elongated direction are formed along a (100) crystal orientation and said termination end surface is formed along a (110) crystal orientation with an surface having a surface shape for forming a end-surface dielectric layer having substantially a same thickness as a dielectric layer formed on said sidewalls. 
 
     
     
         19 . The trenched MOSFET power transistor of  claim 14  wherein:
 said MOSFET power transistor is a N-channel MOSFET power transistor and said trench having a bottom surface formed along a (110) crystal orientation to form a single thermally grown oxide layer thereon having a greater thickness than a single thermally grown oxide layer on said sidewalls to reduce a gate-to-drain capacitance. 
 
     
     
         20 . A trenched MOSFET power transistor comprising a gate disposed in a trench formed in an active cell area of a semiconductor substrate wherein:
 said trench constituting an elongated stripe further comprising sidewalls along an elongated direction of said elongated stripe formed along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe having a significantly less areas than said sidewalls along said elongated direction formed along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and   said trench further comprising an dielectric layer covering said sidewalls and said termination end surface wherein said dielectric layer having different formation growth rates along said first crystal orientation and said second crystal orientation wherein said end surface having significant less areas for reducing effects caused by said different formation growth rate along said second crystal orientation.   
     
     
         21 . The trenched MOSFET power transistor of  claim 20  wherein:
 said sidewall are formed along a (110) crystal orientation and said termination end surface is formed along a (100) crystal orientation for increasing a device performance improvement because of sidewalls formed along said (110) crystal orientation and a single thermally grown dielectric layer having a substantially same thickness on said sidewalls and said termination end surface whereby device performance differences arising from said end surface formed along said (100) crystal orientation may are reduced. 
 
     
     
         22 . The trenched MOSFET power transistor of  claim 20  wherein:
 said MOSFET power transistor is a P-channel MOSFET power transistor and said sidewalls formed along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance; and 
 said trench constituting said elongated stripe further comprising a trench bottom formed along a (100) trench bottom surface covered by a single thermally grow oxide layer having substantially a same thickness as an oxide layer covering said sidewalls. 
 
     
     
         23 . The trenched MOSFET power transistor of  claim 20  wherein:
 said MOSFET power transistor is a N-channel MOSFET power transistor and said sidewall along said elongated direction are formed along a (100) crystal orientation and said termination end surface is formed with a curve end surface to form a thicker dielectric layer thereon along a (110) crystal. 
 
     
     
         24 . The trenched MOSFET power transistor of  claim 20  wherein:
 said MOSFET power transistor is a N-channel MOSFET power transistor and said trench having a bottom surface formed along a (110) crystal orientation to form a thicker oxide layer thereon than an single thermally grown oxide layer covering said sidewalls to reduce a gate-to-drain capacitance. 
 
     
     
         25 . The trenched MOSFET power transistor of  claim 20  wherein:
 said dielectric layer is a single thermally grown oxide layer having a substantially a same thickness covering said sidewalls and said termination end surface of said trench wherein termination end surface formed along said second crystal orientation having a round sidewall surface in order to form a single thermally grown oxide layer to have said substantially a same thickness covering said termination end surface formed along said first crystal orientation. 
 
     
     
         26 . A method for manufacturing a trenched MOSFET power transistor by forming a trench in a semiconductor substrate and then forming a gate in said trench wherein:
 said step of forming said trench further comprising a step of forming said trench with sidewalls along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate and forming a trench bottom surface along a second crystal orientation different from said first crystal orientation of said semiconductor substrate; and   forming a single thermally grown gate oxide layer covering said sidewalls and said bottom surface of said trench having a substantially same gate oxide thickness.   
     
     
         27 . The method of  claim 26  further comprising a step of:
 manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor with said sidewalls surface along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device a reduced on-resistance wherein said bottom surface of said trench is covering with said single thermally grown oxide layer substantially of a same thickness as said single thermally grown oxide layer on said sidewalls whereby a device performance of said MOSFET is not adversely affected. 
 
     
     
         28 . A method for manufacturing a trenched MOSFET power transistor by forming a trench in a semiconductor substrate and then forming a gate in said trench wherein:
 said step of forming said trench further comprising a step of forming said trench with sidewalls along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate and a trench bottom surface along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and   covering said sidewalls and said bottom surface with a single thermally grown dielectric layer having different formation rates on said side wall and said trench bottom having substantially a same thickness on said sidewalls and said bottom surface.   
     
     
         29 . The method of  claim 28  further comprising a step of:
 forming at least one of said sidewall along a (110) crystal orientation and said bottom surface along a (100) crystal orientation having a round bottom surface wherein said dielectric layer having a lower thickness formation rate on said bottom surface than said sidewall surface wherein said round bottom surface providing an enhanced geometry to form said dielectric layer having said substantially thickness on said bottom surface as said dielectric layer on said sidewalls. 
 
     
     
         30 . The method of  claim 28  further comprising a step of:
 manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor and forming said sidewalls surface along a (110) crystal orientation and said round bottom surface along a (100) crystal orientation. 
 
     
     
         31 . The method of  claim 28  further comprising a step of:
 forming at least one of said sidewalls along a (100) crystal orientation having a round sidewall surface and said bottom surface along a (110) crystal orientation with said dielectric layer having a lower thickness formation rate on said sidewalls than on said bottom surface wherein said round sidewall surface providing an enhanced geometry to form said dielectric layer having said substantially thickness on said sidewall surface as said dielectric layer on said bottom surface. 
 
     
     
         32 . A method for manufacturing an N-channel MOSFET power device having a trench comprising:
 forming sidewalls of said trench along a (100) crystal orientation and a trench bottom surface along a (110) crystal orientation and thermally growing a single oxide layer on said sidewalls and said trench bottom surface wherein said trench bottom surface having a thicker layer of said single oxide layer covering said trench bottom surface for reducing a gate-to-drain capacitance.   
     
     
         33 . A method for manufacturing a trenched MOSFET power transistor by forming a trench in an active cell area of a semiconductor substrate and then forming a gate in said trench wherein:
 said step of forming said trench further comprising a step of forming said trench as an elongated stripe with sidewalls along an elongated direction along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe having a curved surface whereby said termination end surface only having a small tip portion formed along a second crystal orientation of said semiconductor substrate different from said first crystal orientation for improving a device performance along said sidewalls formed in said first crystal orientation and reducing device performance differences arising from said second crystal orientation on said small tip portion.   
     
     
         34 . The method of  claim 33  further comprising a step of:
 forming said sidewall along a (110) crystal orientation and said termination end surface along a (100) crystal orientation for increasing a device performance improvement because of sidewalls formed along said (110) crystal orientation having significantly greater area than area of said end surface and also for reducing device performance differences arising from said end surface formed along said (100) crystal orientation. 
 
     
     
         35 . The method of  claim 33  further comprising a step of:
 manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor and forming said sidewalls along a (110) crystal orientation of said semiconductor substrate with said substantially greater area than said area of said end surface for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance. 
 
     
     
         36 . The method of  claim 33  further comprising a step of:
 forming said MOSFET power device as an N-channel device and forming said sidewall along said elongated direction along a (100) crystal orientation and said termination end surface along a (110) crystal orientation having a substantially smaller area than said sidewalls. 
 
     
     
         37 . The method of  claim 33  further comprising a step of:
 manufacturing said MOSFET power transistor as a N-channel MOSFET power transistor by forming said sidewall along said elongated direction along a (100) crystal orientation and forming said trench bottom surface along a (110) crystal orientation for increasing a oxide layer thickness thereon to reduce a gate-to-drain capacitance. 
 
     
     
         38 . A method for manufacturing a trenched MOSFET power transistor by forming a trench in an active cell area of a semiconductor substrate and then forming a gate in said trench wherein:
 said step of forming said trench further comprising a step of forming said trench as an elongated stripe with sidewalls along an elongated direction of said stripe along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe having a significantly less areas than said sidewalls along said elongated direction along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and   forming a single dielectric layer covering said sidewalls and said termination end surface wherein said dielectric layer having different formation growth rates along said first crystal orientation and said second crystal orientation wherein said end surface having significant less areas than said sidewalls for reducing effects caused by said different formation growth rate along said second crystal orientation.   
     
     
         39 . The method of  claim 38  further comprising a step of:
 forming said sidewall along a (110) crystal orientation and said termination end surface along a (100) crystal orientation for improving a device performance because of sidewalls formed along said (110) crystal orientation and for reducing device performance differences arising from said end surface formed along said (100) crystal orientation having significant less areas than said sidewalls. 
 
     
     
         40 . The method of  claim 38  further comprising a step of:
 manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor and forming said sidewalls along a (110) crystal orientation of said semiconductor substrate having a sidewall area significant greater than an area of said end surface for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance. 
 
     
     
         41 . The method of  claim 38  further comprising a step of:
 forming said MOSFET power transistor as an N-channel MOSFET power transistor and forming said sidewall along said elongated direction along a (100) crystal orientation and said termination end surface along a (110) crystal orientation wherein said end surface having significantly less area than said sidewall. 
 
     
     
         42 . The method of  claim 38  further comprising a step of:
 manufacturing said MOSFET power transistor as a N-channel MOSFET power transistor and forming said trench with a bottom surface formed along a (110) crystal orientation to form a single thermally grown oxide layer thereon having a greater thickness than a single thermally grown oxide layer on said sidewall to reduce a gate-to-drain capacitance.