Single transistor memory device having source and drain insulating regions and method of fabricating the same

Abstract

A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

1 . A single transistor floating-body dynamic random access memory (DRAM) device, comprising:
 a floating body located on a semiconductor substrate, the floating body comprising an excess carrier storage region;   a gate electrode located on the floating body;   source and drain regions respectively located at both sides of the gate electrode, each of the source and drain regions contacting the floating body; and   leakage shielding patterns located between the floating body and the source and drain regions.   
     
     
         2 . The device according to  claim 1 , wherein the leakage shielding patterns are arranged at outer sides of the gate electrode. 
     
     
         3 . The device according to  claim 1 , wherein the leakage shielding patterns contact bottom surfaces of the source and drain regions. 
     
     
         4 . The device according to  claim 3 , wherein the floating body is positioned between the source and drain regions, and laterally extends under the leakage shielding patterns. 
     
     
         5 . The device according to  claim 1 , wherein the leakage shielding patterns comprise at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. 
     
     
         6 . The device according to  claim 1 , wherein a width of the excess carrier storage region is larger than a width of the gate electrode. 
     
     
         7 . The device according to  claim 1 , wherein the floating body comprises a single crystal semiconductor layer having p-type impurity ions. 
     
     
         8 . The device according to  claim 1 , further comprising:
 a buried insulating layer located between the semiconductor substrate and the floating body.   
     
     
         9 . The device according to  claim 1 , further comprising:
 an isolation layer defining the floating body, the leakage shielding patterns contacting the isolation layer.   
     
     
         10 . The device according to  claim 1 , wherein the semiconductor substrate is configured to serve as a back gate electrode.