Schottky barrier tunnel transistor and method for fabricating the same

Abstract

A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

1 . A Schottky barrier tunnel transistor comprising:
 a gate electrode formed over a channel region of a substrate to form a Schottky junction with the substrate; and   source and drain regions formed in the substrate exposed on both sides of the gate electrode.   
     
     
         2 . The Schottky barrier tunnel transistor of  claim 1 , wherein the gate electrode comprises one of a metal-based layer and a metal silicide-based layer, wherein the metal-based layer comprises one of a transition metal and a rare earth metal, and the metal silicide-based layer comprises a material obtained by conjugating the metal-based layer and the substrate together. 
     
     
         3 . The Schottky barrier tunnel transistor of  claim 1 , wherein the source and drain regions comprise a metal silicide-based material. 
     
     
         4 . The Schottky barrier tunnel transistor of  claim 1 , wherein the source and drain regions comprise one of a metal-based layer and a metal silicide-based layer, wherein the metal-based layer comprises one of a transition metal and a rare earth metal, and the metal silicide-based layer comprises a material obtained by conjugating the metal-based layer and the substrate together. 
     
     
         5 . The Schottky barrier tunnel transistor of  claim 1 , wherein the substrate comprises one of a silicon-on-insulator (SOI) substrate and a bulk substrate. 
     
     
         6 . The Schottky barrier tunnel transistor of  claim 5 , wherein the silicon-on-insulator substrate comprises:
 a support substrate used to provide a mechanical support;   a buried oxide layer formed over the support substrate; and   a silicon layer formed over the buried oxide layer.   
     
     
         7 . The Schottky barrier tunnel transistor of  claim 6 , wherein the source and drain regions are formed such that a bottom portion of the source and drain regions contacts an upper portion of the buried oxide layer. 
     
     
         8 . The Schottky barrier tunnel transistor of  claim 1 , further comprising spacers formed on sidewalls of the gate electrode. 
     
     
         9 . The Schottky barrier tunnel transistor of  claim 8 , wherein the source and drain regions are self-aligned in the substrate by the spacers.