US2011076812A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: LEE CHOONG-HOPriority: Jul 12, 2007Filed: Dec 3, 2010Published: Mar 31, 2011
Est. expiryJul 12, 2027(~1 yrs left)· nominal 20-yr term from priority
H10W 72/30H10W 72/07331H10W 72/354H10D 30/69H10D 30/798H10D 30/791H10D 30/472H10D 62/405H10D 84/0128H10D 84/038H10B 43/30H10B 41/30H10B 41/35H10W 72/073
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Claims

Abstract

A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.

Claims

exact text as granted — not AI-modified
1 . A method of manufacturing a semiconductor device, the method comprising:
 forming a plurality of cell transistors extending on a first surface of a first substrate in a direction;   preparing a second substrate having a bent upper surface; and   contacting the bent upper surface of the second substrate to a second surface of the first substrate opposite to the first surface to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors.   
     
     
         2 . The method of  claim 1 , wherein the plurality of cell transistors are arranged on a fringe substrate having a { 110 } crystal plane in a growing direction of single crystalline silicon to extend in the { 110 } crystal plane. 
     
     
         3 . The method of  claim 1 , wherein the plurality of cell transistors are arranged on a fringe substrate having a { 100 } crystal plane in a growing direction of single crystalline silicon to extend in the { 100 } crystal plane. 
     
     
         4 . The method of  claim 1 , wherein forming of each of the plurality of cell transistors comprises sequentially forming a tunnel oxide layer, a floating gate electrode, a dielectric layer and an upper electrode on the first surface of the first substrate. 
     
     
         5 . The method of  claim 1 , wherein forming of each of the plurality of cell transistors comprises sequentially forming a tunnel oxide layer, a charge trapping layer pattern, a dielectric layer and an upper electrode on the first surface of the first substrate. 
     
     
         6 . The method of  claim 1 , wherein the bent upper surface of the second substrate has a convex shape in a direction substantially the same as the extending direction of the plurality of cell transistors. 
     
     
         7 . The method of  claim 1 , wherein the bent upper surface of the second substrate has a concave shape in a direction substantially perpendicular to the extending direction of the plurality of cell transistors. 
     
     
         8 . The method of  claim 1 , wherein attaching of the first substrate and the second substrate to each other comprises providing an adhesive between the second surface of the first substrate and the bent upper surface of the second substrate. 
     
     
         9 . The method of  claim 8 , wherein the adhesive comprises an epoxy resin.

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