Semiconductor Devices and Methods of Forming the Same

Abstract

Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be to adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.

1 - 10 . (canceled) 
     
     
         11 . A method of forming a semiconductor device, comprising:
 preparing a semiconductor substrate having a cell array region and a peripheral circuit region;   forming first and second cell gate patterns and a preliminary peripheral gate pattern on the semiconductor substrate, the first and second cell gate patterns being formed in the cell array region and the preliminary peripheral gate pattern being formed in the peripheral circuit region to be adjacent to the second cell gate pattern and to surround the cell array region;   forming cell spacers on sidewalls of the first and second cell gate patterns and the preliminary peripheral gate pattern;   forming buried insulating patterns around the first cell gate pattern, and between the first and second cell gate patterns and the preliminary peripheral gate pattern;   forming mask patterns on the first and second cell gate patterns, and the preliminary peripheral gate pattern;   forming a defining pattern between the cell array region and the peripheral circuit region, and a peripheral gate pattern in the peripheral circuit region to be aligned with the mask patterns, the defining pattern being disposed between the second cell gate pattern and the peripheral gate pattern; and   forming planarization insulating patterns surrounding the peripheral gate pattern.   
     
     
         12 . The method of  claim 11 , further comprising forming isolation regions defining a cell active region of the cell array region and a peripheral active region of the peripheral circuit region,
 wherein the first and second cell gate patterns are respectively formed on the cell active region and the isolation regions, the respective first and second cell gate patterns have a lower cell gate electrode, an upper cell gate electrode and a cell gate capping pattern, which are sequentially stacked, the peripheral gate pattern is disposed on the peripheral active region and has a lower peripheral gate electrode, an upper peripheral gate electrode and a peripheral gate capping pattern, which are sequentially stacked, and the preliminary peripheral gate pattern is disposed on the isolation regions and the peripheral active region and has a lower peripheral conductive layer, an upper peripheral conductive layer and a peripheral gate capping layer, which are sequentially stacked.   
     
     
         13 . The method of  claim 12 , wherein forming the mask patterns comprises:
 sequentially forming a lower mask layer, an intermediate mask layer and an upper mask layer that cover the first and second cell gate patterns, the preliminary peripheral gate pattern, the buried insulating patterns and the cell spacers;   forming photoresist patterns on the upper mask layer, wherein one of the photoresist patterns covers the cell array region and its end is disposed between the second cell gate pattern and the preliminary peripheral gate pattern, and the other photoresist pattern is disposed in the peripheral circuit region to overlap the peripheral active region;   sequentially etching the upper and intermediate mask layers using the photoresist patterns as an etch mask to form upper and intermediate mask patterns, wherein the photoresist patterns are removed from the upper mask patterns while the intermediate mask patterns are formed; and   etching the lower mask layer using the upper and intermediate mask patterns as an etch mask to form a lower mask pattern.   
     
     
         14 . The method of  claim 13 , wherein forming the defining pattern and the peripheral gate pattern comprises:
 partially etching the cell spacer in the cell array region using the upper, intermediate and lower mask patterns as an etch mask to form a cell space pattern corresponding to the defining pattern;   etching the peripheral capping layer and the upper peripheral conductive layer in the peripheral circuit region using the upper, intermediate and lower mask patterns as an etch mask to simultaneously form the peripheral gate capping pattern and the upper peripheral gate electrode together with the cell space pattern, wherein the upper and intermediate mask patterns are removed from the lower mask patterns while the peripheral gate capping pattern, the upper peripheral gate electrode and the cell space pattern are formed; and   etching the lower peripheral conductive layer using the lower mask patterns and the cell space pattern as an etch mask to form the lower peripheral gate electrode below the upper peripheral gate electrode.   
     
     
         15 . The method of  claim 14 , further comprising forming peripheral spacers on sidewalls of the selected lower mask pattern and the buried insulating pattern to be disposed on the defining pattern of the cell array region, and sidewalls of the other lower mask pattern and the peripheral gate pattern to be disposed in the peripheral circuit region. 
     
     
         16 . The method of  claim 15 , wherein forming the planarization insulating patterns comprises:
 forming a planarization insulating layer covering the peripheral spacers and the lower mask layers to fill between the second cell gate pattern and the peripheral gate pattern; and   performing a planarization process on the planarization insulating layer, the lower mask patterns, and the peripheral spacers to expose the first and second cell gate patterns, the peripheral gate pattern, and the buried insulating patterns.   
     
     
         17 . The method of  claim 12 , wherein forming the mask patterns comprises:
 sequentially forming a lower mask layer, an intermediate mask layer, and an upper mask layer that cover the first and second cell gate patterns, the preliminary peripheral gate pattern, the buried insulating patterns and the cell spacers;   forming photoresist patterns on the upper mask layer, wherein one of the photoresist patterns extends from the cell array region and partially overlaps the preliminary peripheral gate pattern, and the other photoresist pattern is disposed in the peripheral circuit region and overlaps the peripheral active region;   sequentially etching the upper and intermediate mask layers using the photoresist patterns as an etch mask to form upper and intermediate mask patterns, wherein the photoresist patterns are removed from the upper mask patterns while the intermediate mask patterns are formed; and   etching the lower mask layer using the upper and intermediate mask patterns as an etch mask to form a lower mask pattern.   
     
     
         18 . The method of  claim 17 , wherein forming the defining pattern and the peripheral gate pattern comprises:
 etching the peripheral capping layer and the upper peripheral conductive layer using the upper, intermediate and lower mask patterns as an etch mask to form an upper dummy gate and a dummy capping pattern, which are sequentially stacked, between the cell array region and the peripheral circuit region, and the upper peripheral gate electrode and the peripheral gate capping pattern, which are sequentially stacked, in the peripheral circuit region, the upper and intermediate mask patterns being removed from the lower mask patterns while the dummy capping pattern, the upper dummy gate, the peripheral gate capping pattern, and the upper peripheral gate electrode are formed; and   etching the lower peripheral conductive layer using the lower mask patterns as an etch mask to form a lower dummy gate below the upper dummy gate and a lower peripheral gate electrode below the upper peripheral gate electrode.   
     
     
         19 . The method of  claim 18 , further comprising forming peripheral spacers on sidewalls of the selected lower mask pattern and the dummy gate pattern to be disposed in the cell array region, and on sidewalls of the other lower mask pattern and the peripheral gate pattern to be disposed in the peripheral circuit region. 
     
     
         20 . The method of  claim 19 , wherein forming the planarization insulating patterns comprises:
 forming a planarization insulating layer covering the peripheral spacers and the lower mask layers to fill between the dummy gate pattern and the peripheral gate pattern; and   performing a planarization process on the planarization insulating layer, the lower mask patterns, and the peripheral spacers to expose the first and second cell gate patterns, the dummy gate pattern, the peripheral gate pattern and the buried insulating patterns.   
     
     
         21 . The method of  claim 12 , wherein forming the buried insulating patterns comprises:
 forming a buried insulating layer covering the cell spacers to fill between the first and second cell gate patterns and the preliminary peripheral gate pattern; and   performing a planarization process on the buried insulating layer to expose the first and second cell gate patterns and the preliminary peripheral gate pattern.   
     
     
         22 . The method of  claim 21 , wherein forming the first and second cell gate patterns and the preliminary peripheral gate pattern comprises:
 sequentially forming a lower conductive layer, an upper conductive layer and a capping layer on the semiconductor substrate;   forming photoresist patterns on the capping layer, wherein a part of the photoresist patterns is disposed in the cell array region to overlap the first and second cell gate patterns, and the other photoresist pattern covers the peripheral circuit region to overlap the preliminary peripheral gate pattern;   sequentially etching the capping layer, the upper conductive layer and the lower conductive layer using the photoresist patterns as an etch mask; and   removing the photoresist patterns from the semiconductor substrate.   
     
     
         23 . A method of forming a semiconductor device, comprising:
 preparing a semiconductor substrate having a cell array region and a peripheral circuit region;   forming a first cell gate pattern in the cell array region, and a preliminary peripheral gate pattern in the peripheral circuit region to be adjacent to the first cell gate pattern to surround the cell array region;   forming cell spacers on sidewalls of the first cell gate pattern and the preliminary peripheral gate pattern;   forming buried insulating patterns between the first cell gate pattern and the preliminary peripheral gate pattern, and around the first cell gate pattern;   forming mask patterns on the first cell gate pattern and the preliminary peripheral gate pattern;   forming a second cell gate pattern in the cell array region and a peripheral gate pattern in the peripheral circuit region to be aligned with the mask patterns; and   forming planarization insulating patterns between the second cell gate pattern and the peripheral gate pattern, and around the peripheral gate pattern.   
     
     
         24 . The method of  claim 23 , further comprising forming isolation regions defining a cell active region of the cell array region and a peripheral active region of the peripheral circuit region,
 wherein the first and second cell gate patterns are respectively disposed on the cell active region and the isolation regions, the first cell gate pattern is formed to have a lower cell gate electrode, an upper cell gate electrode, and a cell gate capping pattern, which are sequentially stacked, the second cell gate pattern is formed to have the other lower cell gate electrode, the other upper cell gate electrode, and the other cell gate capping pattern, which are sequentially stacked, the peripheral gate pattern is formed to be disposed on the peripheral active region and to have a lower peripheral gate electrode, an upper peripheral gate electrode, and a peripheral gate capping pattern, which are sequentially stacked, and the preliminary peripheral gate pattern is disposed on the device isolation regions and the peripheral active region and has a lower peripheral conductive layer, an upper peripheral conductive layer, and a peripheral capping layer, which are sequentially stacked.   
     
     
         25 . The method of  claim 24 , wherein forming the mask patterns comprises:
 sequentially forming a lower mask layer, an intermediate mask layer and an upper mask layer that cover the first cell gate pattern, the preliminary peripheral gate pattern, the buried insulating patterns and the cell spacers;   forming photoresist patterns on the upper mask layer, wherein one of the photoresist patterns is disposed in the cell array region to partially overlap the preliminary peripheral gate pattern by extending from the first cell gate pattern, and the other photoresist pattern is disposed in the peripheral circuit region to overlap the peripheral active region;   etching the upper and intermediate mask layers using the photoresist patterns as an etch mask to form upper and intermediate mask patterns, wherein the photoresist patterns are removed from the upper mask patterns while the intermediate mask patterns are formed; and   etching the lower mask layer using the upper and intermediate mask patterns as an etch mask to form a lower mask pattern.   
     
     
         26 . The method of  claim 25 , wherein forming the second cell gate pattern and the peripheral gate pattern comprises:
 etching the peripheral capping layer and the upper peripheral conductive layer using the upper, intermediate and lower mask patterns as an etch mask to form the other upper cell gate electrode and the other cell gate capping pattern, which are sequentially stacked, in the cell array region, and to form the upper peripheral gate electrode and the peripheral gate capping pattern, which are sequentially stacked, in the peripheral circuit region, wherein the upper and intermediate mask patterns are removed from the lower mask patterns while the other upper cell gate electrode, the other cell gate capping pattern, the upper peripheral gate electrode, and the peripheral gate capping pattern are formed; and   etching the lower peripheral conductive layer using the lower mask patterns as an etch mask to form the other lower cell gate electrode and the lower peripheral gate electrode.   
     
     
         27 . The method of  claim 26 , further comprising forming peripheral spacers on sidewalls of the selected lower mask pattern and the second cell gate pattern to be disposed in the cell array region, and sidewalls of the other lower mask pattern and the peripheral gate pattern to be disposed in the peripheral circuit region. 
     
     
         28 . The method of  claim 27 , wherein forming the planarization insulating patterns comprises:
 forming a planarization insulating layer covering the peripheral spacers and the lower mask layers to fill between the second cell gate pattern and the peripheral gate pattern; and   performing a planarization process on the planarization insulating layer, the peripheral spacers and the lower mask patterns to expose the first and second cell gate patterns, the peripheral gate pattern, and the buried insulating patterns.   
     
     
         29 . The method of  claim 28 , wherein forming the buried insulating patterns comprises:
 forming a buried insulating layer covering the first cell gate pattern, the preliminary peripheral gate pattern and the cell spacers to fill between the first cell gate pattern and the preliminary peripheral gate pattern; and   performing a planarization process on the buried insulating layer to expose the first cell gate pattern and the preliminary peripheral gate pattern.   
     
     
         30 . The method of  claim 29 , wherein forming the first cell gate pattern and the preliminary peripheral gate pattern comprises:
 sequentially forming a lower conductive layer, an upper conductive layer and a capping layer on the semiconductor substrate;   forming photoresist patterns on the capping layer, wherein one of the photoresist patterns is disposed in the cell array region to overlap the first cell gate pattern, and the other photoresist pattern covers the peripheral circuit region to overlap the preliminary peripheral gate pattern;   sequentially etching the capping layer, the upper conductive layer and the lower conductive layer using the photoresist patterns as an etch mask; and   removing the photoresist patterns from the semiconductor substrate.