US2011084247A1PendingUtilityA1

Self-Aligned Bipolar Junction Transistors

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Assignee: PELLIZZER FABIOPriority: Apr 26, 2006Filed: Dec 16, 2010Published: Apr 14, 2011
Est. expiryApr 26, 2026(expired)· nominal 20-yr term from priority
H10D 84/401H10D 84/0109H10D 84/038H10D 10/051H10B 63/10H10N 70/8828H10B 63/32H10N 70/826H10N 70/8413H10N 70/231
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Claims

Abstract

A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit comprising:
 a plurality of bipolar transistors, each transistor including a common conduction region, a control region, and a second conduction region, and at least one control contact region for said plurality of transistors;   a plurality of silicide protection strips; and   silicide regions on said second conduction regions and said one control contact region, aligned with said silicide protection strips.   
     
     
         2 . The circuit of  claim 1  wherein said second conduction regions and control contact region are aligned with said silicide protection strips. 
     
     
         3 . The circuit of  claim 2  wherein said control region extends in an active area on said common conduction region. 
     
     
         4 . The circuit of  claim 3  including a semiconductor body having a surface and field isolation regions of dielectric material in said body, said field isolation regions defining a plurality of active areas, isolated from each other. 
     
     
         5 . The circuit of  claim 4  including an insulating layer above said semiconductor body and contact plugs extending through said insulating layer and in contact with said second conduction regions and said control contact region. 
     
     
         6 . The circuit of  claim 5  including a semiconductor body, said common conduction region extending in said body at a distance from a surface of said body and at least in part below said field isolation regions. 
     
     
         7 . The circuit of  claim 1  wherein said circuit includes a phase change memory. 
     
     
         8 . The circuit of  claim 7  including complementary metal oxide semiconductor transistors.

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