US2011089533A1PendingUtilityA1

Semiconductor device

43
Assignee: RENESAS ELECTRONICS CORPPriority: Jan 28, 2008Filed: Dec 22, 2010Published: Apr 21, 2011
Est. expiryJan 28, 2028(~1.5 yrs left)· nominal 20-yr term from priority
H10D 64/516H10D 62/157H10D 30/65H10D 84/811H10D 84/83H10D 84/835
43
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Claims

Abstract

An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through then epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Claims

exact text as granted — not AI-modified
1 - 4 . (canceled) 
     
     
         5 . A semiconductor device having an output element formation region, an other element formation region, an first active barrier region arranged between said output element formation region and said other element formation region, and a second active barrier region arranged so that said first active barrier region is positioned between said output element formation region and said second active barrier region, comprising:
 a semiconductor substrate having a main surface;   a first region of a first conductivity type formed in said semiconductor substrate in said output element formation region, said other element formation region, said first active barrier region, and said second active barrier region; and   an active barrier structure in each of said first and second active barrier regions, said active barrier structure having a second region of the first conductivity type and a third region of the second conductivity type, each of which is in contact with said first region and which are ohmic-connected to each other to attain a floating potential.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein said second active barrier region surrounded said other element formation region. 
     
     
         7 . The semiconductor device according to  claim 5 , further comprising an another output element formation region, and a third active barrier region arranged between said output element formation region and said another output element formation region.

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